Page 162 - ARM Based Microcontroller Projects Using MBED

148 8. INTERMEDIATE LEVEL PROJECTS

completing executing the ISR, the CPU returns and continues to the point where it left before
the interrupt occurred. When an interrupt occurs, the CPU normally saves the contents of
some registers (e.g., the program counter and status registers) so that it can retrieve them
and continue after returning from the ISR. This is called Context Saving.
On the Cortex-M-based advanced RISC machines (ARM) processors interrupts are man-
aged by the nested vectored interrupt controller (NVIC) which can handle and manage several
hundreds of external as well as internal interrupt requests.
Some important properties of interrupts are:

• Interrupts can be prioritized and as a result they can be nested. What this means is that
different interrupt sources can be given different priority levels so that when multiple
interrupts occur at the same time, the one at the highest priority is handled and executed
first. Also, an executing interrupt can be interrupted by a higher-priority interrupt. When
the higher-priority interrupt completes executing its ISR, control returns to the lower
priority pending interrupt.
• Interrupts can be masked so that, for example, unwanted interrupts from interrupt sources
can be disabled. A disabled interrupt source cannot interrupt the CPU.
• ISR routines start from specific locations in memory, called the interrupt vector addresses.

8.5 PROJECT 3—FOUR-DIGIT 7-SEGMENT LED COUNTER
8.5.1 Description

The problem of using a multiplexed 7-segment LED in a microcontroller is that the CPU
has to refresh the display at regular intervals (e.g., at every 5ms) and as a result of this, the
CPU cannot do other tasks. One way round this problem is to use a timer ISR at 5ms intervals
and refresh the display inside this timer interrupt routine. In this project, the display will
count up every second from 0 to 9999.

8.5.2 Aim

The aim of this project is to show how the 7-segment LED display code can be inserted
inside to a timer ISR so that the display is refreshed in the background. This way, the CPU
is free to do other tasks.

8.5.3 Block Diagram

The block diagram of the project is as in Fig. 8.7.

8.5.4 Circuit Diagram

The circuit diagram of the project is as in Fig. 8.8.

8.5.5 The PDL
The PDL of the program is shown in Fig. 8.14.