Page 307 - Analog and Digital Filter Design
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304 Analog and Digital Filter Design




                        within the passband, but it will have a steeper rate of  attenuation outside the
                        passband.

                        The filter order is required next and this can be an odd number, between three
                        and nine. Filter sections with a high order will have a greater degree of  rejec-
                        tion to signals in the other section’s passband.

                        The load impedance (for both filter sections) is required. Any integer value from
                        “1” to ‘’10,000” can be entered. As described in Chapter 8, each filter section is
                        designed for zero source impedance, but when the two sections are combined
                        the input impedance remains constant and equal to the load. The source is there-
                        fore required to have the same impedance as both loads, which are also equal.

                        The cutof‘f  frequency must be entered next, as a  number and exponent (e.g.,
                        1.7e5 representing  170kHz). This  is the  frequency where  one filter  section’s
                        passband  stops and the other filter section’s passband begins. If  a passband
                        stopband option was chosen, a second cutoff frequency is requested, which must
                        be higher than the one entered previously. The passband of one filter section is
                        defined by  these frequency limits. The other filter section passes all signal fre-
                        quencies outside these limits.

                        The output from this program is a display of  the circuit’s component values.
                        Included is a  description of  their connection in  the two ladder networks. A
                        circuit netlist is produced and saved in a file, “diplexer.ckt,” that will be over-
                        written if  the user decides to design a new diplexer.


                  Match2A

                        The Match2A program allows users to match  a  source to a  load. When  the
                        program is run, the user is asked to enter a value for R1 (the source). A numer-
                        ical value (e.g., 50) should be entered. Next, the user is asked for a value for R2
                        (the load). Again, a numerical value (e.g., 100) should be entered.

                        Once the source and load are entered, the program needs to know the frequency
                        range over which matching is required. The start frequency (in Hertz) needs to
                        be  entered first, say  le6 (for 1MHz). The stop frequency needs to be entered
                        next, say 2e6 (for 2MHz). The VSWR  limit, which is the maximum VSWR
                        within the frequency range specified, should now be entered (e.g., 2.0).
                        The load may be complex and have a  series or shunt reactance included. To
                        allow for this the program asks for the load type (L or C or none). Enter “none”
                        if the load is a pure resistance. If the load has series or parallel inductance, enter
                        the letter L.  If  the load has  series or parallel capacitance, enter the letter C.
                        Suppose you enter the letter C. The program will then ask whether the reactance
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