Page 409 - Complete Wireless Design

Communications System Design

408 Chapter Nine

exists to perform the required functions, or if volume production makes it eco-
nomically viable to actually design and manufacture the RFIC itself—an
extremely expensive option.

An RFIC design consideration. For some portable wireless devices, the receiv-
er’s front-end RFIC (consisting of a conversion stage and RF and IF amplifiers)
may have high-impedance outputs, which interface with external discrete IF
filters. These high impedances are adopted to decrease current drain for the
chip, which can become quite heavy because the RFIC’s built-in IF impedance
matching output buffer is attached to a normal 50-ohm circuit. Thus, the
RFIC’s output may be connected to an external high-impedance IF filter (of a
few thousand ohms) in order to decrease this drain, or with the internal buffer
bypassed altogether and directly attached to a high impedance.
To explain further: For the lowest current drain possible in any amplifier
stage, there is a nominal output impedance, which will depend on the voltage
of the power supply and the RFIC’s output IP3 requirements. (This is exactly
the same idea behind increasing the efficiency in any power amplifier). In oth-
er words, the RFIC buffer’s output intercept point will be governed by the
impedance of its load (R ), and the buffer’s own current consumption (I ), or:
L Q
2
R I
L
Q
OIP3 ≈ 40 10 log
10 2
where OIP3 third output intercept point, dBm
R impedance of the RFIC buffer’s load
L
I RFIC buffer’s current consumption
Q
This demonstrates that the higher the buffer’s current consumption and/or
the higher the load resistance, the higher the OIP3. By increasing the load
resistance, it can be seen that the buffer current can be safely decreased while
maintaining the desired OIP3—an important consideration in most portable
applications.
As an example of the current savings that can be realized with the above
technique, a front-end receiver chip from RFMD, the RF2418 (Fig. 9.10), which
combines an LNA, mixer, and IF buffer on a single chip, will draw 15 mA from
a 3 V DC supply with a 3-dB NF, a 7 dBm IP3, and a 18-dB gain into a
50-ohm filter. However, if the IF output of this buffered chip is connected to a
500-ohm load, the gain will not only increase to 24 dB, but the RFIC’s current
draw will drop to 6.5 mA.
Why do RFIC designers even bother adding this problematic buffer stage?
Because these engineers are able to efficiently match only the naturally high
output impedance of the RFIC to the normally low input impedance of an
external filter with this active buffer stage—instead of applying bulky passive
LC matching. However, as stated above, the matching buffer will consume a
lot of power if a low output impedance is used, which is why some low-power
RFICs will have these high-impedance output ports instead of the normal 50-

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