Page 220 - Electrical Engineering Dictionary

ration of the manipulator) a corresponding the type of transfer requested (read or write).
position and orientation of the end-effector. The transfer is then completely handled by
k : Q → E where Q and E are called, re- the DMA controller, and the CPU is typically
spectively, the inertial (joint) space and the notified by an interrupt when the transfer ser-
external space of the manipulator. Suppose vice is completed. While the DMA transfer
that a manipulator has r-revolute and (n−r) is in progress, the CPU can continue execut-
prismatic joints. Then the internal space is ing the program doing other things. How-
r
r
definedasQ = T ×R n−r , whereT denotes ever, as this may cause access conflicts of the
the r dimensional torus, and R n−r (n−r) di- busses between the CPU and the DMA con-
mensional space of real numbers. troller, a “memory bus controller” handles
prioritized bus requests from these units. The
direct mapped See direct mapped cache. highest priority is given to the DMA trans-
fer, since this normally involves synchronous
direct mapped cache a cache where each data transfer that cannot wait (e.g., a disk or
main memory (MM) block is mapped di- tape drive). Since the CPU normally origi-
rectly to a specific cache block. Since the nates the majority of memory access cycles,
cache is much smaller than the MM, several the DMA control is considered as “stealing”
MM blocks map to the same cache block. bus cycles from the CPU. For this reason, this
If, for example, the cache can hold 128 technique is normally referred to as “cycle
blocks, MM block k will map onto cache stealing.”
block k modulo 128. Because several MM
blocks map onto the same cache block, con- directmethod Lyapunov’ssecondmethod
tention may arise for that position. This is of investigating the stability of dynamical
resolved by allowing the new block to over- systems. The method is called a direct
write the old one, making the replacement method because no knowledge of the solu-
algorithm very trivial in this case. tion of the differential equations modeling a
In its implementation, a high-speed ran- dynamical system is required when investi-
dom access memory is used in which each gatingthestabilityofanequilibriumsolution.
cache line and the most significant bits of its See also equilibrium solution and stability.
main memory address (the tag) are held to-
gether in the cache at a location given by the direct method coordination coordina-
least significant bits of the memory address tion by the direct method amounts to iterating
(theindex). Afterthecachelineisselectedby the coordination variables (direct coordina-
its index, the tag is compared with the most tion instruments) defined as the interaction
significant bits of the required memory ad- inputs and outputs and, if needed, any other
dress to find whether the line is the required variables that, when fixed, provide for inde-
line and to access the line. pendenceofthelocaldecisionproblems. The
results of these problems are used by the co-
direct memory access (DMA) used in ordinator to check whether its objectives are
a computer system when transferring blocks satisfied — if not, then the direct coordinat-
of information between I/O devices (e.g., ing instruments are changed (iterated), etc.
disk memory) to/from the main memory
with minimal intervention from the CPU. A direct modulation modulation of the op-
“DMA controller” is used and can, after initi- tical intensity output from a semiconductor
ation by the CPU, take control of the address, diode laser by direct modulation of the bias
control, and data busses. The CPU initiates current.
the DMA controller with parameters such as
the start address of the block in main mem- direct scattering theory predicts the dis-
ory, number of bytes to be transferred, and tribution of scattered intensity from knowl-

c
2000 by CRC Press LLC