Page 155 - Embedded Microprocessor Systems Real World Design

In processors that do not have a stack limited by hardware, there is still a
limitation: the size of the system RAM. Make sure that the code cannot make the
stack grow into the area where variables are stored. This problem can be hard to
find.
Getting around a limited stack sometimes requires programming finesse that
bends the normal rules a bit. The usual practice for a subroutine is to save all the
registers on the stack; some high-level languages do this automatically. This can be
impractical if there are several subroutines.
The simplest workaround is not to save anything. The polling loop just knows
which registers are used by the subroutine and assumes they will be changed. Values
can be returned in registers as well. The pool timer code has subroutines that do
not save registers.
In cases where registers must be saved, they can be stored in RAM as variables.
Each subroutine has a block of RAM set aside for storing registers. Each register
that must be saved is stored in a unique RAM location on entry to the subroutine
and retrieved on exit. Of course, this method prevents the subroutine from being
reentrant.
Some processors make provision for a context switch. The Analog Devices
ADSPBlOl family, for example, has two complete register sets. Either may be
selected by a single instruction. The 8051 has four register banks. Two bits in an
internal register control which register bank is in use. In processors like these, each
subroutine can have a unique register set. However, there is a drawback as well: The
Analog Devices parts have only one extra register set, so only one subroutine can
be handled without saving registers into RAM. The 8051 has four register sets, which
limits the code to four unique environments. Many compilers can take advantage
of these features of the CPU.

Chip Select

Some processors have internal chip selects that can be programmed. If this hard-
ware is used, it must be initialized first. As an example, look at the 80188 again.
This part has a signal, -UCS, which is a chip select to upper memory, intended to
select an EPROM or flash memory. After a reset, -UCS is programmed to access
the upper 1 K of memory from FFCOO to FFFFF. If the actual EPROM is 32K X 8,
the software at the reset vector location (FFFFO) must initialize -UCS to select the
full 32K before jumping to any location below the upper 1 K. Otherwise, the
EPROM will not be selected and the processor will go off into the weeds. Staying
with the 80188 example, the signal -LCS is intended to select RAM from location
00000 up. Reset turns this signal off, and it must be programmed before it will be
active .
The implication of this is that, in a system using -LCS and -UCS, no subroutine
calls can be made, nor can any interrupts be serviced, until both signals are

136 Embedded Mim@n-ocessor Systems