Page 107 - A Practical Guide from Design Planning to Manufacturing

82 Chapter Three

designs are derived from earlier designs, and a great deal can be learned
about a design by looking at its family tree. Because different proces-
sor designs are often sold under a common marketing name, tracing the
evolution of designs requires deciphering the design project names. For
design projects that last years, it is necessary to have a name long before
the environment into which the processor will eventually be sold is
known for certain. Therefore, the project name is chosen long before the
product name and usually chosen with the simple goal of avoiding trade-
mark infringement.
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Figure 3-4 shows the derivation of the AMD Athlon designs. Each box
shows the project name and marketing name of a processor design with
the left edge showing when it was first sold.
The original Athlon design project was called the K7 since it was AMD’s
seventh generation microarchitecture. The K7 used very little of previous
AMD designs and was fabricated in a 250-nm fabrication process. This
design was compacted to the 180-nm process by the K75 project, which
was sold as both a desktop product, using the name Athlon, and a server
product with multiprocessing enabled, using the name Athlon MP. Both
the K7 and K75 used slot packaging with separate SRAM chips in the
same package acting as a level 2 cache.
The Thunderbird project added the level 2 cache to the processor die
eventually allowing the slot packaging to be abandoned. A low cost ver-
sion with a smaller level 2 cache, called Spitfire, was also created. To
make its marketing as a value product clear, the Spitfire design was
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given a new marketing name, Duron .
The Palomino design added a number of enhancements. A hardware
prefetch mechanism was added to try and anticipate what data would
be used next and pull it into the cache before it was needed. A number
of new processor instructions were added to support multimedia oper-
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ations. Together these instructions were called 3D Now! Professional.
Finally a mechanism was included to allow the processor to dynamically
scale its power depending on the amount of performance required by the
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current application. This feature was marketed as Power Now! .
The Palomino was first sold as a mobile product but was quickly
repackaged for the desktop and sold as the first Athlon XP. It was also
marketed as the Athlon MP as a server processor. The Morgan project
removed three-fourths of the level 2 cache from the Palomino design to
create a value product sold as a Duron and Mobile Duron.
The Thoroughbred and Applebred projects were both compactions
that converted the Palomino and Morgan designs from the 180-nm gen-
eration to 130 nm. Finally, the Barton project doubled the size of the
Thoroughbred cache. The Athlon 64 chips that followed were based on
a new lead design, so Barton marked the end of the family of designs
based upon the original Athlon. See Table 3-5.