Page 130 - A Practical Guide from Design Planning to Manufacturing
P. 130

Computer Architecture  103

               TABLE 4-7  Relative Instruction Count
        Architectural type          Instruction count
        Pure register                    198%
        Register/memory                  178%
        Pure memory                      114%





        architecture, which can provide more compact code. The RISC archi-
        tectures are three-operand architectures. The VAX architecture, seek-
        ing the greatest possible flexibility in instruction type, provides for both
        two- and three-operand formats.
          The number and type of operands supported by different instructions
        will have a great effect on how these instructions can be encoded.
        Allowing for different operand encoding can greatly increase the func-
        tionality and complexity of a computer architecture. The resulting size
        of code and complexity in decoding will have an impact on performance.

        Data transfer instructions
        In addition to computational instructions, any computer architecture
        will have to include data transfer instructions for moving data from
        one location to another. Values may be copied from main memory to the
        processor or results written out to memory. Most architectures define
        registers to hold temporary values rather than requiring all data to be
        accessed by a memory address. Some common data transfer instructions
        and their mnemonics are listed in Table 4-8.
          Loads and stores move data to and from registers and main memory.
        Moves transfer data from one register to another. The conditional move
        only transfers data if some specific condition is met. This condition
        might be that the result of a computation was 0 or not 0, positive or not
        positive, or many others. It is up to the computer architect to define all
        the possible conditions that can be tested. Most architectures define a
        special flag register that stores these conditions. Conditional moves can



        TABLE 4-8  Data Transfer Instructions
        LD        Load value from memory to a register
        ST        Store value from a register to memory
        MOV       Move value from register to register
        CMOV      Conditionally move value from register to register if
                  a condition is met
        PUSH      Push value onto top of stack
        POP       Pop value from top of stack
   125   126   127   128   129   130   131   132   133   134   135