Page 263 - A Practical Guide from Design Planning to Manufacturing

Circuit Design 235

they merely have a certain probability of being within a particular volume
of space. This volume is large enough that in transistors with gate oxides
less than 5-nm thick, there is a significant probability that an electron
that started on one side of the gate oxide might appear on the other side.
If there is an electric field, the electron will be pulled away from the gate
oxide and be unable to get back. The result is a flow of electrons, a cur-
rent, through the gate oxide. This phenomenon is called gate tunneling
current or just gate leakage.
The easiest way to control gate leakage is to use a thicker gate oxide,
but this will reduce the on current of the transistor unless the electric per-
mittivity of the gate oxide (e ) can be increased. New high-K gate dielec-
ox
tric materials seek to increase gate permittivity to allow for more on
current without increasing gate leakage. Tunneling currents set a lower
limit on how thin an insulator can be and still effectively block current
flow. Even if a 1-molecule-thick gate oxide layer could be manufactured,
its high leakage would probably make it impractical for use.
In the same way a designer can trade off noise immunity for speed,
most circuits can easily be made faster at the cost of higher power. Higher
voltages, larger device widths, and lower threshold voltages, all enable
higher frequencies but at some cost in power. Modern processor designs
must carefully analyze timing, noise, and power and consider the inter-
actions between them to perform successful circuit design.

Conclusion
The processor’s circuit design gives a complete description of all the tran-
sistors to be used and their connections, but in order to be fabricated these
transistors must be converted into layout. Creating layout is discussed
in detail in the next chapter, but some aspects of circuit design depend
upon layout. Sizing gates requires knowing what their output capacitance
is, and this capacitance will come in part from wires. The length of the
wires will be determined by the relative placement of gates and the over-
all size of the layout. The cross talk noise on wires is affected by the spac-
ing to its neighboring wires and whether these wires can switch at the
same time. This will also be determined by layout. The capacitance of the
wires will have a large contribution to active power.
To perform circuit design, some assumptions must be made about the
layout. This is called prelayout circuit design. The circuit designer and
mask designer together plan out the overall topology of a circuit block,
so that the various wire lengths and spacings can be estimated. Timing,
noise, and power checks are then performed using these estimates. The
initial circuit design is then created in layout.
Postlayout circuit design then begins. All the checks done prelayout
must be performed again to make sure the initial assumptions about the