Page 428 - Power Electronic Control in Electrical Systems

//SYS21/F:/PEC/REVISES_10-11-01/075065126-APPENDIX.3D ± 407 ± [407±426/20] 17.11.2001 4:39PM

Appendix

This appendix presents the settings of the most relevant blocks used in the digital implementa-
tions developed in PSCAD/EMTDC,for each of the FACTS and Custom Power controllers
considered in Chapter 8.
SVC

TITLE: SVC_FACTS
TIME-STEP: 3.5e-05
FINISH-TIME: 0.4
PRINT-STEP: 0.0005
RTDS-RACK: 0
RTDS REAL-TIME: Yes

SVC test power circuit (Figure 8.17)

Single-Phase Source
Mag : 13.8 kV
f : 50
Initial Phase : 0.0
Ramp up time : 0.0001 [sec]
Timed Breaker Logic
Initial State : Open
Time of First Breaker Operation : 0.6 [sec]

SVC controller (Figure 8.18)

PI Controller
Gp : 2500
Ti : 0.001
Hard Limiter
Upper limit : 65.0
Lower limit : 20