Page 37 - Power Electronics Handbook

30 Power semiconductor devices

when a second breakdown effect develops. This results in rapid local
heating of the silicon die, the collector-emitter voltage collapses, and the
current escalates, destroying the transistor. There is a series of curves for
different base currents and these give rise to individual second breakdown
points, which all lie on a locus, as shown. As the duty cycle of the transistor
decreases it runs cooler so that it can work on a wider second breakdown
locus.
Power transistors must be operated in a mode such that second
breakdown is avoided. This is done using the safe operating area (SOA)
curves, of the type shown in Figure l.l3(b). Although these curves are for
a device rated at a peak current of ZM and a voltage of VM, the transistor
cannot be run at this current and voltage simultaneously. For low values of
VcE the current can increase to lM, where it is limited by the
current-carrying capability of the bonding wire and the metallisation tracks
used on the silicon. As V, increases so also does the power dissipation, 50
that eventually ZC will need to be decreased. For large values of V, the
value of Zc is reduced still further in order to prevent the occurrence of
second breakdown effects. The SOA of the transistor increases as the duty
cycle reduces, since both the dissipation and second breakdown effects are
now lower.

1.5.3 Construction
Several different construction techniques are used for power transistors,
each giving some advantage, such as high voltage ratings or speed of
operation. Figure 1.14 shows a few of these.
In the mesa structure the junction area is reduced by a mesa etch, so that
junction capacitances are decreased. This technique also allows the edges
of the transistor, mainly the collector-base junction, to be defined and
passivated, which prevents contamination, so avoiding high electric fields.
The hometaxial structure is easy to produce so that it is cheap and
rugged. It has good overall voltage ratings but suffers from relatively long
switching times.
The epi-base transistor generally has a relatively low voltage rating, but
this can be increased by adding high-resistivity collector epitaxy. This
causes the collector voltage to be shared by the base and collector epitaxy
layers, but the voltage rating is still less than for hometaxial. The process
uses shallow emitter diffusions and a narrow-base epitaxy, so. it has higher
speed and current-handling capability than a hometaxial transistor for the
same emitter area.
The planar epitaxial arrangement has all its junctions protected during
fabrication by an oxide layer, so it is capable of being designed for very low
leakage current. The diffusion process also enables very narrow base
widths to be built, thus giving higher speeds and lower saturation voltage
drops than hometaxial or epi-base transistors. The disadvantage of the
planar epitaxial device is that it is not very resistant to the effects of second
breakdown.
The triple-diffused transistor is better than planar on second breakdown,
but it is still not very resistant to this. Speed and saturation voltage drops
are similar to planar epitaxial, but the construction is more expensive and