Page 429 - Programming Microcontrollers in C

414 Chapter 8 MCORE, A RISC Machine

The use of this table is similar to that shown with the MC68HC16
family. Here, though, we will concentrate on the use of the autovector.
The autovector is accessed when an interrupt is called with the
autovector line to the core processor asserted. When this type of
interrupt is executed, control of the processor is automatically
transferred to the function addressed contained in the autovector
vector. Note in the table that there are two autovector locations, the
normal autovector and the fast autovector. The DIAB compiler
automatically encodes interrupts to use the fast autovector, so the
offset vector location is 0x2c from the Vector Base Address.
The MMC2001 has an internal peripheral called the Interrupt
Controller. This device handles all interrupt sources from the on-
board peripherals. There are several 32-bit registers in the Interrupt
Controller. You will notice in the MMC2001 Reference Manual,
Section 10, that these registers are each just collections of 32 single
bits. These registers control interrupts. The first register is called the
Interrupt Source Register, INTSCR. Whenever an interrupt is
requested by this controller, it is assigned a level from 0 to 32 and the
corresponding bit in the INTSCR is set. There are two interrupt enable
registers: Normal Interrupt Enable, NIER and Fast Interrupt Enable,
FIER. The program must set the corresponding bit in one of these
registers to enable an interrupt to be detected.
When an interrupt is requested, the corresponding bit in the
INTSCR is set and this register is automatically ORed with the
Interrupt Enable registers. The results of these operations are stored
in the proper Interrupt Pending Register. These registers, NIPND
and FIPND, then contain a bit pattern that show all of the pending
interrupts for the system.
There is one very convenient instruction available in the MCORE
instruction set. This instruction, FF1, indicates “find the first 1 set” in
a memory location. This instruction uses the system barrel shifter and
requires only one clock cycle. The priority of the several interrupting
sources is established by their individual bit locations in the various
registers in the controller. In the FIPND registers, bit 31 contains the
status of the highest priority pending interrupt, etc. When the FF1
instruction is executed on the FIPND, the result identifies the bit number
of the highest priority pending fast interrupt. Table 8-2 shows the
interrupt assignments of all on-board peripherals on this chip.