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420    Chapter 8  MCORE, A RISC Machine

                          clock is driven by the low-frequency oscillator frequency divided by
                          128 or 256 Hz. The watchdog and the PIT are both driven by the
                          low-frequency oscillator frequency divided by 4 or 8196 Hz. The
                          TOD keeps track of the time as the number of seconds since a specified
                          time, perhaps midnight. There is no provision for automatic roll­
                          over of the registers at the end of the day, so if you want to work
                          from midnight each day, you must reset the TOD clock to zero each
                          midnight. This clock also has an 8-bit fractional second register in
                          addition to the regular 32-bit second count register.
                              The alarm system also contains an 8-bit fractional second register
                          and a 32-bit second register. When the time in the alarm registers
                          matches the time in the time of day register, a flag is set that can be
                          polled or an interrupt can be requested.
                              The PIT system contains a register that is counted down. When
                          this register underflows, it can be reloaded automatically, set a flag
                          to be polled, or request an interrupt. Loading this register is done
                          through a register called the ITDR, the Interval Timer Data Register.
                          If a bit is set, data written to the ITDR will automatically transfer to
                          the ITADR, the register that counts down. When this register
                          underflows, the contents of the ITDR is automatically transferred to
                          the ITADR. The contents of the ITDR can be changed at any time,
                          and it can be changed without altering the contents of the ITADR
                          until the next underflow.
                              The ITADR is clocked 8192 times per second, approximately 122
                          microseconds. Since it is clocked an exact number of times per second,
                          it is possible to count in exact second intervals. It makes no difference
                          how you break up the time intervals, the clock will decrement exactly
                          8192 times in one second. Therefore, if you want a basic interval time
                          for other uses in the system, you can cause interrupts to occur at this
                          faster rate and then count the number of interrupts until you achieve
                          the magic number of 8192 ticks each second. For example, many
                          systems need a 1 or 2 millisecond time interval. The system can be set
                          to interrupt about every 2 milliseconds and then in the ISR, a counter
                          incremented. This counter counts to about 500 each second and can be
                          easily used in a clock controller. Of course, “about” is not allowed.
                          The interrupt time must be 0.001953125 seconds and there will be
                          exactly 512 interrupts per second.
                              The program starts out with the creation of a function that we
                          will call keep_time().This function is executed repeatedly inside
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