Page 337 - Satellite Communications, Fourth Edition

Error Control Coding 317

when n 3. A binary 1 at the input to the encoder results in a 111 code-
word at the output, and a binary 0 at the input results in a 000 codeword
at the output. At the receiver, the logic circuits in the decoder produce a
1 when 111 is present at the input and a 0 when 000 is present. It is
assumed that synchronization is maintained between encoder and
decoder. If a codeword other than 111 or 000 is received, the decoder
detects an error and can request a retransmission (ARQ).
FEC can take place on the basis of a “majority vote.” In this case, the
logic circuits in the decoder are designed to produce a 1 at the output
whenever two or three 1s occur in the received codeword (codewords 111,
101, 011, and 110) and a 0 whenever two or three 0s appear in the code-
word (codewords 000, 001, 010, and 100). An odd number of “repeats”
is used to avoid a tied vote.
Errors can still get through if the noise results in two or three suc-
cessive errors in a codeword. For example, if the noise changes a 111 into
a 000 or a 000 into a 111, the output will be in error whether error
detection or FEC is used. If two errors occur in a codeword, then the
“majority vote” method for FEC will result in an error. However, the
probability of two or three consecutive errors occurring is very much less
than the probability of a single error. This assumes that the bit energy
stays the same, an aspect that is discussed in Sec. 11.7. Codes that are
more efficient than repetitive encoding are generally used in practice.
As a matter of definition, a code is termed linear when any linear com-
bination of two codewords is also a codeword. For binary codewords in
particular, the linear operation encountered is modulo-2 addition. The
rules for modulo-2 addition are:

0 0 0 0 1 1 1 0 1 1 1 0

Modulo-2 addition is easily implemented in hardware using the exclusive-
OR (XOR) digital circuit, which is one of its main advantages. All codes
encountered in practice are linear, which has a bearing on the theo-
retical development (see Proakis and Salehi, 1994).
To illustrate this further consider the eight possible datawords formed
from a 3-bit sequence. One parity bit will be attached to each dataword
as shown in the Table 11.1. The parity bits are selected to provide even
parity, that is, the number of 1s in any codeword is even (including the
all-zero codeword). The parity bits are found by performing a modulo-2
addition on the dataword.
With even parity it is seen that the bits in the codeword modulo-2 sum
to zero. It would be possible to use odd parity where the parity bit is
chosen so that the modulo-2 sum of the codeword is 1, however this
would exclude the all-zero codeword. A linear code must include the all-
zero codeword, and hence even parity is used.