Page 12 - ARM 64 Bit Assembly Language
P. 12

List of figures





                     Fig. 1.1  Simplified representation of a computer system.                          1
                     Fig. 1.2  Stages of a typical compilation sequence.                               3
                     Fig. 1.3  Tables used for converting between binary, octal, and hexadecimal.     12
                     Fig. 1.4  Four different representations for binary integers.                    14
                     Fig. 1.5  Complement tables for base ten and base two.                           16
                     Fig. 1.6  A section of memory can be viewed in different ways.                   28
                     Fig. 1.7  Typical memory layout for a program with a 32-bit address space.       29
                     Fig. 2.1  Equivalent static variable declarations in Assembly and C.             40
                     Fig. 3.1  A simplified view of the AArch64 architecture.                          54
                     Fig. 3.2  AArch64 general purpose registers (R0-R30) and special registers.      55
                     Fig. 3.3  Fields in the PSTATE register.                                         56
                     Fig. 5.1  AArch64 User Program Registers.                                       128
                     Fig. 6.1  Binary tree of word frequencies.                                      168
                     Fig. 6.2  Binary tree of word frequencies with index added.                     174
                     Fig. 6.3  Binary tree of word frequencies with sorted index.                    175
                     Fig. 7.1  In signed 8-bit math, 11011001 2 is −39 10 .                          194
                     Fig. 7.2  In unsigned 8-bit math, 11011001 2 is 217 10 .                        195
                     Fig. 7.3  Multiplication of large numbers.                                      197
                     Fig. 7.4  Longhand division in decimal and binary.                              198
                     Fig. 7.5  Flowchart for binary division.                                        199
                     Fig. 8.1  Examples of fixed point signed arithmetic.                             253
                     Fig. 9.1  AArch64 Integer (left) and FP/NEON (right) User Program Registers.    294
                     Fig. 9.2  With the FP/NEON instructions, parts of register Vn can be accessed by using
                               different views. Each view has a unique name.                         295
                     Fig. 9.3  Bits in the FPCR.                                                     296
                     Fig. 9.4  Bits in the FPSR.                                                     298
                     Fig. 10.1  All of the possible views for register Vn. Valid names depend on which instruction is
                               being used.                                                           324
                     Fig. 10.2  Pixel data interleaved in thee doubleword registers.                 327
                     Fig. 10.3  Pixel data de-interleaved in thee doubleword registers.              327
                     Fig. 10.4  Examples of the trn instruction.                                     338
                     Fig. 10.5  Transpose of a 3 × 3 matrix.                                         339
                     Fig. 10.6  Example of zip1 v1.8h,v5.8h,v6.8h.The zip2 instruction does the same thing,
                               but uses the odd elements of the source registers, rather than the even elements.  339
                     Fig. 10.7  Effects of sli v4.2d,v9.2d,#6.                                       378



                                                              xi
   7   8   9   10   11   12   13   14   15   16   17