Page 382 - ARM 64 Bit Assembly Language

372 Chapter 10

• F/Tc must be h/h or s/s.
• If Tc is h,then Vc must be in the range v0-v15.

10.7.8.2 Operations

Name Effect Description
sqdmull Fd ← Fn × Vm[x]× 2 Multiply, double the results, sat-
urate, and store in the destination
register.

sqdmlal Fd ← Fd + Fn × Vm[x]× 2 Multiply elements, double the re-
sults, add to the destination register,
and saturate.
sqdmlsl Vd[] ← Fd − Fn × Vm[x]× 2 Multiply elements, double the re-
sults, subtract from the destination
register, and saturate..
sqdmulh Fa ← Multiply, double the results, satu-
Fb × Vc[x]× 2 n rate, and store the high half in the
destination register.
sqrdmulh Fa ← Multiply elements, double the re-
Fb × Vc[x]× 2 n sults, round, saturate, and store
the high half in the destination
register.

10.7.8.3 Examples

1 sqdmull d1,s6,v8.s[1] // Multiply, double, saturate
2 sqdmlal s0,h4,v5.h[0] // Multiply double, saturate, accumulate
3 sqdmlal s0,h4,h5 // Alias for previous instruction

10.8 Shift instructions

The Advanced SIMD shift instructions operate on vectors. Shifts are often used for mul-
tiplication and division by powers of two. The results of a left shift may be larger than the
destination register, resulting in overflow. A shift right is equivalent to division. In some cases,
it may be useful to round the result of a division, rather than truncating. Advanced SIMD
provides versions of the shift instruction which perform saturation and/or rounding of the re-
sult.