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8.3 PROJECT 2—FOUR-DIGIT MULTIPLEXED 7-SEGMENT LED 141
FIG. 8.7 Block diagram of the project.
FIG. 8.8 Circuit diagram of the project.
Fig. 8.7. Fig. 8.8 shows the project circuit diagram. All the corresponding a–g pins of the four
digits are connected together and are driven from the lower byte of PORT C (PC_0–PC_6)
through 390 ohm current limiting resistors. The four-digit enable pins are controlled using
two BC108-type NPN transistors (any other NPN-type transistor can be used here). GPIO
pin PC_8, PC_9, PC_10, and PC_11 control the digits as shown in Fig. 8.8. When the base
of the transistor is set to logic 1, the corresponding transistor is switched ON and thus its col-
lector becomes at logic 0 which enables the corresponding digit. A digit is disabled if the base
of the corresponding transistor is at logic 0.
8.3.5 The PDL
Fig. 8.9 shows the operation of the program as a PDL.