Page 71 - Building A Succesful Board-Test Strategy

Jest Methods 57

and expensive. Most board manufacturers performed incoming inspection, believ-
ing the order-of-magnitude rule that finding bad parts there would cost much less
than finding them at board test.
For as long as the number of VLSI types remained small, device manufac-
turers, tester manufacturers, or a combination of the two created test-program
libraries to exercise the devices during board test. Custom-designed parts presented
more of a problem, but high costs and lead times of 15 months or longer dis-
couraged their use.
More recently, computer-aided tools have emerged that facilitate both the
design and manufacture of custom logic. Lead times from conception to first
silicon have dropped to a few weeks. Manufacturers replace collections of jellybean
parts with application-specific integrated circuits (ASICs). These devices improve
product reliability, reduce costs and power consumption, and open up board real
estate to allow shrinking products or adding functionality.
In many applications, most parts no longer attach to the board with leads
that go through to the underside, mounting instead directly onto pads on the board
surface. Adding to the confusion is the proliferation of ball-grid arrays (EGAs),
flip chips, and similar parts. In the interest of saving space, device manufacturers
have placed all nodes under the components themselves, so covered nodes have pro-
gressed from a rarity to a major concern. Ever-increasing device complexity also
makes anything resembling a comprehensive device test at the board level imprac-
tical, at best. Today's microprocessors, for example, cram millions of transistors
onto pieces of silicon the size of pocket change.
Board manufacturers have found several solutions. To deal with nodes on
both board sides, some use "clamshell" beds-of-nails, which contact both board
sides simultaneously. Clamshells, however, will not help to test EGAs and other
hidden-node parts. Other approaches create in-circuit tests for circuit clusters,
where nodes are available, rather than for single devices. Although this method
permits simpler test programming than functionally testing the entire board does,
the nonstandard nature of most board clusters generally defies automatic program
generation. To cope with the challenges, strict design-for-testability guidelines
might require that design engineers include test nodes, confine components to one
board side, and adopt other constraints. For analog circuitry, new techniques have
emerged that allow diagnosing failures with less than full access.
As manufacturing processes improved, in-circuit-type tests often uncovered
few defects, and a larger proportion fell into the category of "functional" failures.
As a result, many manufacturers returned to functional testing as their primary
test tactic of choice to provide comprehensive verification that the board works as
designers intended without demanding bed-of-nails access through nodes that do
not exist.
Unfortunately, proponents of this "new" strategy had to contend with the
same problems that led to its fall from grace in the first place. Functional testers
can be expensive. Test programming remains expensive and time-consuming, and
fault diagnostics can be very slow. Complicating matters further is the fact that
electronic products' selling prices have dropped precipitously over the years, while