Page 283 - Electrical Engineering Dictionary

field-effect transistor (FET) a majority- (2) a gate array with a programmable
carrier device that behaves like a bipolar tran- multi-level logic network. Reprogramma-
sistor with the important difference that the bility of FPGAs make them generic hard-
gate has a very high input impedance and ware and allow them to be reprogrammed to
therefore draws no current. serve many different applications. FPGAs
An active device with three terminals — consist of SRAMS, gates, latches, and pro-
gate, source, and drain — in the active (am- grammable interconnects.
plifier) mode of operation, the drain current is
related to the gate-source voltage. The rela- FIFO See first-in-first-out.
tionship is usually approximated by a square
law, but there are significant deviations from FIFO memory commonly known as a
the square law depending on factors such as queue. It is a structure where objects are
device geometry. The FET can also be used taken out of the structure in the order they
as a switch, with the gate-source voltage con- were put in. Compare this with a LIFO mem-
trolling the “on/off” state of the conducting ory or stack. A FIFO is useful for buffering
channel between source and drain terminals. data in an asynchronous transmission where
The input resistance at the gate is extremely the sender and receiver are not synchronized:
high (usually of order tens of megaohms) and the sender places data objects in the FIFO
the gate current is negligibly small (usually memory, while the receiver collects the ob-
of order picoamperes or less). jects from it.
There are various families of FETs, in-
figure of merit performance evaluation
cluding MOSFETs and JFETs. Within each
measure for the various target and equipment
family, there are two types of FET, n-channel
parameters of a sonar system. It is a subset of
and p-channel (named for the sign of the ma-
the broader sonar performance given by the
jority carriers that form the current conduct-
sonar equations, which includes reverbera-
ing path between source and drain).
tion effects.
Some FETs also have a fourth terminal,
the “substrate” or “body” terminal. The p-
file format the structure of the computer
n junctions between the substrate and the
file in which an image is stored. Often the
drain and source terminals should be reverse-
format consists of a fixed-size header fol-
biased to insure proper device operation.
lowed by the pixel values written from the
top to the bottom row and within a row
field-oriented control speed control of
from the left to the right column. However,
an induction motor obtained by varying the
it is also common to compress the image.
magnitude and orientation of the airgap mag-
SeealsoGraphicsInterchangeFormat, header,
netic field. This is also referred to as vector
image compression, tagged image file format
control and requires sensing of the rotor po-
(TIFF).
sition. Vector controllers allow the induction
motor to operate very much like a DC mo-
Filippov method a definition of a solution
tor, including development of rated torque at
to a system of first-order differential equa-
zero speed.
tions with discontinuous right-hand side,
field-programmable gate array (FPGA) ˙ x = f(t, x),
(1) a programmable logic device that consists
of a matrix of programmable cells embedded proposed by A. F. Filippov. A vector func-
in a programmable routing mesh. The com- tion x(t) defined on the interval [t 1 ,t 2 ] is
bined programming of the cell functions and a solution to the above system of differen-
routing network define the function of the de- tial equations in the sense of Filippov, if it
vice. is absolutely continuous and for almost all
c
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