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fully associative cache memory and in some  (2) in contrast with a symmetric multipro-
                              translation look-aside buffers or page transla-  cessor, asymmetric multiprocessor is a mul-
                              tion tables of the hardware to support virtual  tiprocessor in which the processors are not
                              memory. Given the user-space address of a  assigned equal tasks. The controller (mas-
                              page it returns the physical address of that  ter) processor(s) are assigning tasks to (slave)
                              page in main memory. Also called content  processors and controlling I/O for them.
                              addressable memory (CAM).
                                                                     asymmetric multivibrator  a multivibra-
                              associative processor  a parallel proces-  tor where the output voltage represents a train
                              sor consisting of a number of processing el-  of narrow pulses. Most asymmetric multivi-
                              ements, memory modules, and input–output  brators use a slow charge of a large timing ca-
                              devices under a single control unit. The ca-  pacitor by a small current (or via a large resis-
                              pability of the processing elements is usually  tor) and a fast discharge of this capacitor via
                              limited to the bit-serial operations.  a switch. The charge process determines the
                                                                     duration of space; the mark duration, which
                              associativity  In a cache, the number of  coincides with the time allowed for discharge
                              lines in a set. An n-way set associative cache  of the timing capacitor, is usually determined
                              has n lines in each set. (Note: the term  by a small time constant of the circuit con-
                              “block” is also used for “line.”)      trolling the switch. Asymmetric multivibra-
                                                                     tors find applications in voltage-to-frequency
                                                                     converters. Also called multivibrators with a
                              astable multivibrator  the circuit that is
                                                                     small mark/space ratio.
                              obtainedfromaclosed-loopregenerativesys-
                              tem that includes two similar amplifiers of
                                                                     asymmetric resonator   standing-wave
                              high gain connected with each other via cou-
                                                                     resonator in which either the reflectivities or
                              pling circuits with reactance elements. More
                                                                     the curvatures of the primary mirrors are un-
                              frequently are used RC-coupling circuits
                                                                     equal.
                              (free-running RC-multivibrators, emitter-
                              coupled multivibrators), yet RL-circuits,
                                                                     asymmetrical silicon controlled rectifier
                              usually as transformer coils, may be used as
                                                                     (ASCR)    (1) an inverter grade SCR fab-
                              well (magnetic multivibrators).
                                                                     ricated to have limited reverse voltage capa-
                                                                     bility. Fabrication with asymmetrical volt-
                              astigmatism  a defect associated with op-
                                                                     age blocking capability in the forward and
                              tical and electrostatic lenses where the mag-
                                                                     reverse direction permits reduction of turn-
                              nification is not the same in two orthogonal
                                                                     on time, turn-off time, and conduction drop.
                              planes; common where beam propagation is
                                                                       (2) a thyristor that has limited conduc-
                              not along the axis of rotation of the system.
                                                                     tion in the reverse direction to gain increased
                                                                     switching speed and low forward voltage
                              asymmetric digital subscriber line (ADSL)
                                                                     drop. See also silicon controlled rectifier
                              a digital subscriber line (DSL) in which the
                                                                     (SCR).
                              rate from central switching office (CO) to
                              customer premise is much faster than the rate
                                                                     asymptotic 2-D observer  a system de-
                              from customer premise to CO.
                                                                     scribed by the equations
                              asymmetric multiprocessor  (1) a ma-
                                                                        z i+1,j+1 = F 1 z i+1,j + F 2 z i,j+1
                              chine with multiple processors, in which the
                                                                                  + G 1 u i+1,j + G 2 u i,j+1
                              time to access a specific memory address is
                              different depending on which processor per-         + H 1 y i+1,j + H 2 y i,j+1
                              forms the request.                            ˆ x i,j = Lz i,j + Ky i,j
                              c 
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