Page 249 - Embedded Microprocessor Systems Real World Design

CPU 1 wants the buffer and reads the flag location to see if the buffer is
free.
CPU 1 finds that the flag is 00, indicating that the buffer is free.
CPU 2 wants the buffer and reads the flag location to see if the buffer is
free.
CPU 2 finds that the flag is 00, indicating that the buffer is free.
CPU 1 writes 01 to the flag location, indicating that it is taking the buffer.
CPU 2 writes 02 to the flag location, indicating that it is taking the buffer.
Now we have a conflict-each CPU thinks it has control of the buffer. But now
we will add the second arbitration step:
CPU 1 checks the flag location again, finds that 02 is there instead of 01,
knows it has lost the arbitration, and waits.
CPU 2 checks the flag location again, finds that 02 is there, and knows it has
the buffer.
Of course, you must handle the case where CPU 2 is a little slow and writes the 02
after CPU 1 has performed the second check. This might occur if CPU 2 has a
slower clock or gets an interrupt between wanting the buffer and asserting control
of the buffer. One way around this is to have a sufficient delay between writing and
checking the buffer to ensure that all the writes are finished.
Another way around the contention issue is to have a three-value flag and inter-
locked handshake. Each CPU has a flag location for the common resource, and
each is assigned a priority.
When one CPU wants the resource, it checks the flags for all the CPUs. Only if
all the flags are zero can it request the resource, by writing 01 to its own flag loca-
tion. Then it checks all the flags again. If a higher-priority CPU has requested the
resource (by writing 01 to its flag location), the lower-priority CPU must wait. It
indicates this by writing 02 to its flag location. If no higher-priority CPUs have
requested the resource, it indicates ownership by writing 03 to its flag location.
If a higher-priority CPU wants the resource, it does the same checks before
writing 01 to the buffer. If a lower-priority CPU has written 01 at the same time, the
higher-priority CPU cannot take the resource until the lower-priority CPU writes
either 02 or 03. If the lower-priority CPU writes 03, the higher-priority CPU was a
little behind and must wait. If the lower-priority CPU writes 02, then the higher-
priority CPU can write 03 and take the resource.
This complicated scheme is needed because there always is a possibility that one
CPU will write 01 to its flag location after the other CPU has read the flags, found
them zero, and written 01. The following are four possible contention scenarios
and how this protocol handles them (CPU 2 has the highest priority in all these
examples). In Scenario 1:

230 Embedded Microprocessor System