Page 224 - Engineering Digital Design

PROBLEMS 195

(a) From the third-order K-map, write the canonical coded SOP and POS for this
function.
(b) Use this K-map to extract the minimum SOP and POS expressions for this function.
4.30 Find the minimum SOP and POS expressions (cover) for each of the following
sub-functions and give the cell location of each sub-function in the fourth-order
K-map.
(a) P(A, B, C, D, E, F, G) = £ m(33, 34, 36, 38) + 0(32, 29)
(b) Q(a, b, c, d, e, /, g, h} = £>(114, 116, 118, 122, 124, 126)
(c) R(A, B, C, D, E, F, G) = H Af(105, 107, 108, 109, 110)
(d) S(a, b, c, d, e, f, g, h) = FJ M(176, 181, 182, 183, 184, 189, 191)
• 0(177, 185, 190)
4.31 Minimize each of the following functions in both SOP and POS form by using the
Quine-McCluskey (Q-M) algorithm discussed in Section 4.8.
(a) /(«;,*, ;y) = J>(0,l, 3, 5, 7)
(b) g(a,b,c) = 0^(2,3,4,6)
(c) F(W, X, 7, Z) = £>(0, 2,4,5,6, 8, 10,11,13, 14)
(d) G(A,B,C, D) = Y\M(l,2,3,5,l,9, 11,12, 14)

4.32 Minimize each of the functions of Problem 4.7 in both SOP and POS form by using
the Quine-McCluskey (Q-M) algorithm discussed in Section 4.8. Keep in mind the
manner in which the Q-M algorithm treats don't cares.
4.33 Minimize each of the functions of Problem 4.8 in both SOP and POS form by using
the Quine-McCluskey (Q-M) algorithm discussed in Section 4.8. Keep in mind the
manner in which the Q-M algorithm treats don't cares.
4.34 Use the method of factorization to obtain a gate-minimum SOP and POS result for
the following two-level functions. Find the gate/input tally (including inverters) for
each and compare the results with the two-level minimum forms. Assume the inputs
all arrive from positive logic sources. (Hint: First minimize the functions in two-level
form and then apply the_ factorization method.)
(a) Y = AB + BD + AC+ABC + ACD
(b) F = ABDE + ABCE + CDE + BCDE + ABCD + (A O C)(B + D)

4.35 Use the resubstitution method discussed in Subsection 4.9.2 to obtain a gate mini-
mum for each of the following functions. Compare the gate/input tally (excluding
inverters) of the result with that for the two-level minimum. Also, comment on fan-in
and inverter requirements for each, and on the gate propagation delay level for each.
Assume that all inputs are active high. (Hint: First obtain the two-level SOP minimum
expression, then plan to use the suggested divisor given for each.)
(a) F(W, X, Y, Z) = £ m(0, 4, 5, 7, 10, 13, 14, 15) (Use divisor X + Z)
(b) G(A,B,C, D) = £>(0, 1,2,3,4,9, 10,11, 13, 14,15)
(Use divisor A + C + D)
(c) H( W, X, Y, Z) = f] M(0, 2, 4, 6, 9) (Your choice of divisor)

4.36 Decompose each function in Problem 4.3 1 by applying Shannon 's expansion theorem
discussed in Subsection 4.9.3. Try at least two sets of two- variable axes about which