Page 163 - Hardware Implementation of Finite-Field Arithmetic

146 Cha pte r S i x

vhd, reduced version of adder_subtractor.vhd). The complete VHDL
file pse-udo_Euclidean_divider.vhd is available at www.arithmetic-
circuits. org. The entity declaration is
entity pseudo_Euclidean_divider is
port(
g, h: in polynomial;
clk, reset, start: in std_logic;
z: out polynomial;
done: out std_logic
);
end pseudo_Euclidean_divider;
The VHDL architecture corresponding to the circuit of Fig. 6.1 is
the following:

long_c(m) <= “00000000”; long_e(m) <= “00000000”;
definition: for i in 0 to m-1 generate
long_c(i) <= c(i); long_e(i) <= e(i);
end generate;
with sel_sub select sub1 <= n_a when ‘0’, long_c when
others;
with sel_sub select nbe <= n_b when ‘0’, long_e when
others;
functions1: for i in 0 to m generate
m1: mod_239_multiplier port map(coef, nbe(i),
sub2(i));
s1: subtractor port map(sub1(i), sub2(i), out1(i));
end generate;
by_x1: for i in 1 to m-1 generate sub3(i) <= e(i-1); end
generate;
sub3(0) <= “00000000”;
functions2: for i in 0 to m-1 generate
m2: mod_239_multiplier port map(e(m-1), f(i),
sub4(i));
s2: subtractor port map(sub3(i), sub4(i), out2(i));
end generate;
dr_minus1 <= deg_r - 1; db_minus1 <= deg_b - 1; dif <=
deg_a - deg_b;
inverter: mod_239_inverter port map(clk, n_b(m), inv_
out);
m3: mod_239_multiplier port map(n_a(m), inv_out, coef);
functions3: for i in 0 to m-1 generate
m4: mod_239_multiplier port map(inv_out, d(i), z(i));
end generate;
by_x2: for i in 1 to m generate nr_by_x(i) <= n_r(i-1);
end generate;
nr_by_x(0) <= “00000000”;
with sel_r select next_r <= out1 when ‘0’, nr_by_x when
others;
with sel_r select next_dr <= deg_a when ‘0’, dr_minus1
when others;
definition2: for i in 0 to m-1 generate