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9.3. Number Systems and Basic Operations 489
9,3. NUMBER SYSTEMS AND BASIC OPERATIONS
Various number systems and corresponding algorithms suitable for optical
implementation have been investigated. Theses number systems can be categor-
ized as binary and nonbinary. In the binary category, number systems with
positive radix such as 2's complement and that with negative radix, named
negabinary, were studied. The nonbinary systems include mixed radix, residue,
and signed-digit number representations. In this section, we briefly discuss the
basic operations of binary number systems and review the operations of
nonbinary number systems.
9.3.1. OPERATIONS WITH BINARY NUMBER SYSTEMS
9.3,1.1. Positive Binary Number System
In conventional binary number systems with radix 2, three representations;
namely, sign magnitude, 1's complement, and 2's complement, were used to
encode a bipolar number. In signed-magnitude representation, the most
significant bit (MSB) is identified as the sign of the number, 0 for positive and
1 for negative numbers. In each step of the operations, the MSB needs to be
dealt with separately. Therefore, it is not suitable for parallel computation. In
1's complement representation, a negative number is formed by a bit-by-bit
complement of the corresponding positive number. This produces two possible
representations for 0, which is not desired. In 2's complement representation,
a negative number is formed by adding 1 to its 1's complement representation.
This technique eliminates the two representations of zero otherwise encoun-
tered with 1's complement representation, and a single addition or subtraction
can be performed without any special concern for signs. Thus, 2's complement
representation is widely used in digital computing. A 2's complement number
may be represented by the following equation:
N 1
X = ~-x N^2 '- + £ x f 2',x,.e{0, 1}, (9.4)
i = 0
where x^_ j is the sign bit. A fractional number can be represented with
negative indices.
Addition is the most fundamental arithmetic operation. Addition of two
/V-bit numbers A and B can be performed by using half-adders or a full-adder
in N iterations. The half-adder is a two-input/two-output logical circuit. The
truth table corresponding to its two inputs a t and />,-, and the outputs,

