Page 556 - Introduction to Information Optics

9.4. Parallel Signed-Digit Arithmetic 541
Table 9.37
Truth Table for the Second Step Operation in
NSD Addition and Subtraction [162]

0 0 1 0
0 1 (1) 1
1 0 ._
0 I (0)
I 0
1 I (0) 0
I 1

The above algorithms for two-step addition and subtraction can be mapped
to the architecture of symbolic substitution or content-addressable memory
(CAM). The logical minterms for the nonzero output are summarized in Table
9.39. Alternatively, one can implement the involved arithmetic through logic
operations. We define the operations with binary logic, but signed digits are
included. A closer look at the truth tables reveals that it is necessary to
introduce two additional reference bits, g ( and h {. For addition, g ( is true if both

Table 9.38
Truth Table for the First Step Operation in NSD
Subtraction [162] where B;_ t Indicates the Complement of &,._,
fl; 6,- (0; /!;)
1 1 (0 0) Don't care 0 0
1 0 (1 0) a,._ j and b t.. ] are (1) 0 1
nonnegative
Otherwise (0) T T
1 I (1 0) Don't care I 0
0 1 (0 0) «(_] and b l_ l are (1) 1 1
nonnegative
Otherwise (0) 0 T
0 0 (1 0) Don't care 0 0
0 I (1 0) a,-^j and ft £_ , are (1) 0 1
nonnegative
Otherwise (0) T I
1 1 (0 1) Don't care ] 0
I 0 (0 0) «,._! and fe,._ j are (1) 1 1
nonnegative
Otherwise (0) 0 T
I T (0 0) Don't care 0 0