Page 15 - Introduction to Microcontrollers Architecture, Programming, and Interfacing of The Motorola 68HC12
P. 15

xiv                                                        List of Figures


                                 List of Figures

        Figure      Title                                                 Page


        Figure 1.1 Simplified Computer Structure                              2
        Figure 1.2 Registers in the 6812                                      5
        Figure 1.3 Registers and Memory                                       9
        Figure 1.4 Data Operator Arithmetic                                   11
        Figure 1.5 Program for 8-Bit Addition                                 11
        Figure 1.6 Bits in the Condition Code Register                       12
        Figure 1.7 Addition of Two-Byte Numbers                              12
        Figure 1.8 Program for 16-Bit Addition                                13
        Figure 1.9 Alternative Program for 16-Bit Addition                    13
        Figure 1.10 Most Efficient Program for 16-Bit Addition                15
        Figure 1.11 Single-Chip Mode of the MC68HC812A4                       16
        Figure 1.12 Expanded Wide Multiplexed Bus Mode of the MC68HC812A4     17
        Figure 1.13 Memory Maps for the 6812                                  17
        Figure 1.14 Single-Chip Mode of the MC68HC912B32                      18
        Figure 1.15 Expanded Wide Multiplexed Bus Mode of the MC68HC912B32   19
        Figure 1.16 Variable Word Width Implementation                       20

        Figure 2.1 A Program Segment to Clear a Byte                         28
        Figure 2.2 A Stack                                                   30
        Figure 2.3 Transfers between Registers                               32
        Figure 2.4 Program Segment to Initialize the Condition Code Register  33
        Figure 2.5 Program Segment for 32-Bit Addition                       35
        Figure 2.6 Multiplication                                            36
        Figure 2.7 Program Segment for 16-Bit Unsigned Multiplication        36
        Figure 2.8 Program Segment for BCD Addition                          37
        Figure 2.9 Program Segment for Conversion from Celsius to Fahrenheit  37
        Figure 2.10 Common Logic Operations                                  38
        Figure 2.11 Bit-by-Bit AND                                           39
        Figure 2.12 Shifts and Rotates                                       40
        Figure 2.13 Shift Hardware                                           41
        Figure 2.14 Program Segment to Swap Nibbles                          41
        Figure 2.15 Program Segment for Insertion of Some Bits               42
        Figure 2.16 Decision Tree                                            44
        Figure 2.17 Program Segment for a Decision Tree                      44
        Figure 2.18 Program Segment for Setting, Clearing, and Testing of a Bit  45
        Figure 2.19 Program Segment for a Wait Loop                          46
        Figure 2.20 Subroutine and Handler Addresses                         47
        Figure 2.21 Program Segment for Swap Subroutine                      47
        Figure 2.22 Program Segment for Ensuring a Value Is between Limits   50
        Figure 2.23 Program Segment for a Multiply and Add Operation         51
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