Page 155 - A Practical Guide from Design Planning to Manufacturing

128 Chapter Five

Introduction

Although a processor’s architecture defines the instructions it can exe-
cute, its microarchitecture determines the way in which those instruc-
tions are executed. Of all the choices made in a processor design flow,
microarchitectural decisions will have the greatest impact on the proces-
sor’s performance and die area. Chapter 4 discussed how changes in
architecture affect performance, but it is possible to build multiple
processors that all support the same architecture with enormously dif-
ferent levels of performance. The difference between such implementa-
tions is their microarchitectures.
By definition, architectural changes are visible to the programmer
and require new software to be utilized. New architectural registers or
SIMD instructions improve performance for programs that use them
but will have no impact on legacy software. Microarchitectural changes
are not visible to the programmer and can improve performance with no
change in software.
Because microarchitectural changes maintain software compatibility,
processor microarchitectures have changed much more quickly than
architectures. Like almost all other changes in the semiconductor indus-
try, Moore’s law has driven this progress. The microarchitectural con-
cepts in use today were not totally unknown to past designers; they
were simply impractical. As Moore’s law allows larger and larger tran-
sistor budgets, old microarchitectural ideas that were too complex to be
implemented become possible.
Imagine writing a word processing program. The program should pro-
vide as much functionality and ease of use as possible, but must be lim-
ited to 10,000 lines of code. With this restriction, this word processor will
be a very crude program indeed. If after two years, a new word proces-
sor is created using twice as many lines of code, there could be signifi-
cant added functionality. If this pattern were to repeat, in 10 years a
word processor written using over 300,000 lines of code might be dra-
matically more sophisticated. This does not mean that the earliest ver-
sion was poorly designed; merely that it had different design constraints.
Growing transistor budgets allow microarchitects more resources to imple-
ment higher performance processors. An early design might include a single
adder whereas a later design might include two, allowing more processing
to occur in parallel. Inevitably other changes are needed to make efficient
use of the ability to execute more instructions in parallel. The most successful
way of performing more work in parallel has been through pipelining.

Pipelining

Most microarchitectural improvements have focused on exploiting
instruction level parallelism (ILP) within programs. The architecture