Page 175 - A Practical Guide from Design Planning to Manufacturing

148 Chapter Five

Modified (M). Processor owns line and copy is different than main
memory.
Exclusive (E). Processor owns line and copy is the same as main
memory.
Shared (S). Processor shares line with others.
Invalid (I). Line is invalid.

These coherency schemes are called MESI protocols after the sup-
ported states. A modified line has been written by the processor, so that
it now holds the only copy of the latest data. The processor must pro-
vide this data if another agents try to read this line. An exclusive line
is held only in one cache but still matches the copy in main memory. A
processor can write this line and change its state to modified, without
notifying other agents. A shared line means the same data is held in
main memory and more than one cache. Any writes to this line must be
broadcast on the bus to allow other processors to update their caches.
An invalid line is typically one that has been written by another proces-
sor making the lines in other caches out of date. Some of these transi-
tions are shown in the example in Fig. 5-12.

Processor A Processor B Main memory
Flag Tag Data Flag Tag Data Addr Data Processor A
I – – E 1 G 1 G starts with an
empty cache
I – – I – – 2 H

Processor A Processor B Main memory
Flag Tag Data Flag Tag Data Addr Data Processor A
S 1 G S 1 G 1 G reads address
1 and 2
E 2 H I – – 2 H

Processor A Processor B Main memory
Flag Tag Data Flag Tag Data Addr Data Processor A
M 1 X I – – 1 G writes address
1 and 2
M 2 Y I – – 2 H

Figure 5-12 Cache coherency transitions.