Page 132 - A Practical Guide from Design Planning to Manufacturing

Computer Architecture 105

TABLE 4-10 Floating-Point Formats
Size Sign Exponent Fraction Binary Decimal
Precision (bits) (bits) (bits) (bits) range range
Single 32 1 8 23 2 −126 to 2 127 1.18 × 10 −38
to 3.40 × 10 38
Double 64 1 11 52 2 −1022 to 2 1023 2.23 × 10 −308
to 1.79 × 10 308
Extended 80 1 16 63 2 −16382 to 2 16383 3.37 × 10 −4932
to 1.18 × 10 4932
Value = 1.<Fraction> × 2 Exponent

Working with floating-point numbers requires more complicated hard-
ware than integers; as a result the latency of floating-point operations
is longer than integer operations. However, the increased range of pos-
sible values is required for many graphics and scientific applications.
As a result, when quoting performance, most processors provide sepa-
rate integer and floating-point performance measurements. To improve
both integer and floating-point performance many architectures have
added single instruction multiple data (SIMD) operations.
SIMD instructions simultaneously perform the same computation on
multiple pieces of data (Fig. 4-1). In order to use the already defined
instruction formats, the SIMD instructions still have only two- or three-
operand instructions. However, they treat each of their operands as a
vector containing multiple pieces of data.
For example, a 64-bit register could be treated as two 32-bit integers,
four 16-bit integers, or eight 8-bit integers. Instead, the same 64-bit
register could be interpreted as two single precision floating-point num-
bers. SIMD instructions are very useful in multimedia or scientific
applications where very large amounts of data must all be processed in
the same way. The Intel MXX and AMD 3DNow! extensions both allow
operations on 64-bit vectors. Later, the Intel Streaming SIMD Extension

Normal (word) SIMD (2 half words) SIMD (4 bytes)
32 b 16 b 16 b 8 b 8 b 8 b 8 b

A A C A C E G
+ + +
B B D B D F H
= = =
A + B A + B C + D A + B C + D E + F G + H
Figure 4-1 SIMD instructions.