Page 134 - A Practical Guide from Design Planning to Manufacturing

Computer Architecture 107

TABLE 4-11 Little Endian versus Big Endian
Little endian Big endian
VAX, x86, EPIC SPARC, PA-RISC, PowerPC

order of a number to convert between the little endian and big endian
formats. In addition, the EPIC, PA-RISC, and PowerPC architectures
all support special modes, which cause them to read data in the oppo-
site format from their default assumption. Any new architecture will
have to pick a side or build in support for both.
Architectures must also decide whether to support unaligned memory
accesses. This would mean allowing a value of more than 1 byte to begin
at any byte in memory. Modern memory bus standards are all more
than 1-byte wide and for simplicity allow only accesses aligned on the
bus width. In other words, a 64-bit data bus will always access memory
at addresses that are multiples of 64 bits. If the architecture forces 64
bit and smaller values to be stored only at addresses that are multiples
of their width, then any value can be retrieved with a single memory
access. If the architecture allows values to start at any byte, it may
require two memory accesses to retrieve the entire value. Later accesses
of misaligned data from the cache may require multiple cache accesses.
Forcing aligned addresses improves performance, but by restricting
where values can be stored, the use of memory is made less efficient.
Given an address, the choice of little endian or big endian will deter-
mine how the data in memory is loaded. This still leaves the question
of how the address itself is generated. For any instruction that allows
a memory operand, it must be decided how the address for that memory
location will be specified. Table 4-12 shows examples of different address-
ing modes.
The simplest possible addressing is absolute mode where the memory
address is encoded as a constant in the instruction. Register indirect
addressing provides the number of a register that contains the address.
This allows the address to be computed at run time, as would be the case

TABLE 4-12 Data Addressing Modes

Address mode Address Typical use
Absolute Const Global variable
Register Indirect Reg Dynamically allocated variable
Displacement Const + Reg(× Size) Array
Indexed Reg + Reg(× Size) Dynamically allocated array
Scaled Const + Reg + Reg(× Size) Two dimensional array
Memory Indirect Mem[Reg] Memory pointers