Page 14 - Modern Control of DC-Based Power Systems

List of Figures xiii

Figure 6.11 ISPS I L1=L2=L3 for Ideal CPL and 30.9 - 53.4 MW 232
Figure 6.12 ISPS V bus for ideal CPL—Step 30.9 - 53.4 MW 235
(Droop PI)
Figure 6.13 ISPS I L1=L2=L3 for ideal CPL and 30.9 - 53.4 MW 235
(Droop PI)
Figure 6.14 ISPS V bus for ideal CPL—generator loss (60 - 40 MW) 235
30.9 MW base load
Figure 6.15 ISPS I L1=L2 for ideal CPL—generator loss (60 - 40 MW) 236
30.9 MW base load
Figure 6.16 Measured and filtered bus voltage of LQG with virtual 238
disturbance—ideal CPL
Figure 6.17 ISPS V bus for switched LRC, ideal CPL—Step 30.9 - 239
53.4 MW load
Figure 6.18 ISPS I L1=L2=L3 for switched LRC, ideal CPL—Step 30.9 - 239
53.4 MW load
Figure 6.19 Duty cycle of all control methods 241
Figure 6.20 Duty cycle of adaptive backstepping with f s 5 1 MHz 241
Figure 6.21 Measurement and estimate—LQG virtual disturbances 242
Figure 6.22 Measurement and estimate back virtual disturbances 242
Figure 6.23 Measured bus voltage and filtered bus voltage for LQG 243
with virtual disturbance—switched CPL representation
Figure 6.24 ISPS V bus for switched LRC, switched CPL—Step 30.9 - 243
53.4 MW load
Figure 6.25 ISPS I L1=L2=L3 for switched LRC, switched 244
CPL—Step 30.9 - 53.4 MW load
Figure 7.1 The HiL setup 250
Figure 7.2 The discretization process 251
Figure 7.3 The implementation of the LQG controller for the HiL 254
simulation of the MVDC ISPS
Figure 7.4 The implementation of the LQG controller in the FPGA 255
Figure 7.5 Load step increase—bus voltage (LQG) 256
Figure 7.6 Load step increase—bus voltage (LSF) 256
Figure 7.7 Converter disconnection—bus voltage (LQG) 257
Figure 7.8 Converter disconnection—bus voltage (LSF) 257