Page 9 - Modern Control of DC-Based Power Systems

viii List of Figures

Figure 2.22 Bode plot of the current control input to output voltage 47
G vc sðÞ:
s ðÞ: 48
Figure 2.23 Bode plot of the voltage control transfer function G c v
Figure 2.24 Bode plot of the inner voltage loop gain T PICM F B ðsÞ with 49
Phase Margin 80 degrees, Delay Maring 0.00222 s, at
f 5 100 Hz, Closed Loop stable 5 No
Figure 2.25 Key features and functions of a network analyzer 49
Figure 2.26 Typical test setup for measuring G vd ðsÞ when the converter 50
operates with constant duty cycle
Figure 2.27 Typical test setup for measuring T VM ðsÞ when the converter 51
operates in VMC
Figure 2.28 Equivalent source subsystem interaction with the equivalent 52
load subsystem (A) and equivalent MIMO feedback block
diagram (B)
Figure 2.29 Stability criteria: boundaries between forbidden regions and 54
allowable regions
Figure 2.30 Averaged model simulation in Simulink of the cascade 56
of a buck converter and a VSI
Figure 2.31 Bode plot of the OL, PICM, and PICM_FB input 57
impedances of the VSI
Figure 2.32 Bode plot of the OL, PICM, and PICM_FB output 58
impedance of the buck converter with resistive load
Figure 2.33 Bode plot of the OL, PICM, and PICM_FB output 59
impedance of the buck converter with resistive load
removed
Figure 2.34 Bode plot of the OL and VM_FB output impedance of the 60
buck converter with resistive load
Figure 2.35 Bode plot of the OL and VM_FB output impedance of the 61
buck converter with resistive load removed
Figure 2.36 Nyquist plot of the minor loop gain for the cascade of 62
PICM_FB-controlled buck converter and PICM_FB-
controlled VSI (stable case)
Figure 2.37 Bus voltage and VSI three-phase output voltage transient in 62
correspondence of a symmetric VSI load step from 20Ω to
10Ω for the cascade of PICM_FB-controlled buck
converter and PICM_FB-controlled VSI (stable case)
Figure 2.38 Nyquist plot of the minor loop gain for the cascade of 63
VM_FB-controlled buck converter and PICM_FB-
controlled VSI (stable case)
Figure 2.39 Bus voltage and VSI three-phase output voltage transient in 63
correspondence of a symmetric VSI load step from 20Ω to
10Ω for the cascade of VM_FB-controlled buck converter
and PICM_FB-controlled VSI (stable case)