Page 261 - Programming Microcontrollers in C

246 Chapter 5 Programming Large 8-Bit Systems

each device. The Ex series has four output compares, three input
captures, and one timer that can be programmed as either output
compare or input capture. The other devices have three input captures
and five output compares.

Output Compare Subsystems
What does an output compare do? The explanation of the timer
subsystem must always begin with the 16-bit timer counter called TCNT
that is always counting at some fraction of the system bus frequency.
The bus frequency is always one-fourth of the system crystal frequency.
The prescaler frequency is set to the bus frequency divided by either 1,
4, 8, or 16 depending on the bits PR1 and PR0 in the register TMSK2.
The timer counter register can be read at any time but it cannot be
written to. The Output Compare 1 is special. All of the discussion that
follows is valid for all output compares, but—as will be shown later—
Output Compare 1 has capability beyond the others.
Associated with each output compare system there is a single
16-bit output compare register containing the time that the program
needs an event to occur. When TCNT contents matches that of OCx,
an OCx event occurs. Note that I say an event, not output. What
happens when the contents of the TCNT matches the contents of OCx
is up to the program. Associated with each output compare is a pin
that can be set, reset, or toggled when an output compare occurs.
When an output compare occurs, the corresponding OCxF flag bit is
set in the TFLG1 register. This bit can be examined asynchronously
by the program to determine whether an output compare has occurred.
If the corresponding bit in the TMSK1 register is set when the OCxF
flag bit is set, an interrupt will be requested by the part and the event
will be processed asynchronously. These are the operations of all
output compare subsystems in the part.
There are three input captures, four output compares, and one
timer that can be programmed as either an output or an input. This
timer is controlled by the I4O5 bit in the PACTL register. When this
bit is a zero, the programmable timer is an output compare. Otherwise
when the bit is set, the programmable timer is an input capture. Often
it is desirable to have an output compare operation be initiated by the
completion of another output compare. Output Compare 1 is set up
in just this manner. The bits in the OC1M and the OC1D registers
control the coupling between the Output Compare 1 and the other