Page 267 - Programming Microcontrollers in C

252 Chapter 5 Programming Large 8-Bit Systems

Notice that this code is very similar to the earlier program shown
in Listing 5-4. The interrupt service handling is set up by use of the
@port construct and the two added instructions which first enable
the OC3 interrupt and then enable the system interrupts. The code
that was contained within the FOREVER loop in Listing 5-4 has been
moved into the interrupt service routine in this program.
This program was run, and it was experimentally determined that
the maximum value that can be allowed for time_on is 0xff0
when period is 0x1000. This maximum value indicates that 16 clock
cycles or 8 microseconds at an 8-MHz crystal is needed to service
the interrupt prior to the occurrence of an OC1. The minimum on
time found here is slightly better than found with the code in Listing
5-4. In this case, the minimum on time is 1 clock cycle, which is the
expected minimum value.
We have already seen that a significant time is required to process
an interrupt, and it is usually impossible to have an output event occur
during the interrupt service routine. With the above code it is easy to
have a minimum on time of one clock cycle. This small time is
accomplished by having the setting of the output signal not be attended
by an interrupt. The interrupt will occur when the output signal is
reset. Therefore, when the coupled output signal with OC1 goes high,
the output compare on the coupled channel will have its event even if
the time is as short as one clock cycle beyond the occurrence of OC1.
Assume that the coupled channel is OC3. When the event occurs on
OC3, an interrupt will occur. In this interrupt service routine, both
OC1 and OC3 will have to be set up to operate in the correct manner.
This operation has a problem with long on times. If the event associated
with OC3 occurs a few clock cycles prior to the occurrence of the OC1
event, and the interrupt is caused by OC3, then the OC1 set-up might
not be completed when the next OC1 time arrives. In this case, the
whole base period would go out of kilter, and there would be at least
one cycle of the output that would be based on the timer overflow
cycle rather than the desired time base.
As is often found in engineering operations, there is a choice that
can be made. If the interrupt is based on the reset time of the PWM
cycle, then a minimum on period of one cycle can be achieved. With
this choice of operation, the maximum on time will be several clock
cycles—perhaps 20 to 30—short of 100% on. On the other hand, if
the interrupt is based on the set time of the PWM cycle, the minimum