Page 339 - Programming Microcontrollers in C

324 Chapter 6 Large Microcontrollers

be stated that the optimizer changes the code suggested by the pro­
grammer. Often when you examine the code generated by the compiler,
the operations that take place will not even resemble those that the
programmer had in mind. This alteration of the code will show up
with shifts, and divides or products of powers of two. A proper optimizer
should determine if a multiply or a shift is better and provide the best
code. Often you will find that the compiler optimizer will provide
either fastest execution or minimum code. Usually the two will be
different. Faster code will almost always take more memory.
It may seem that the lost time is small, but you will always find
that if you want fast code, you will not use any looping constructs. The
code that increments a counter and tests the counter must be executed
each loop. Without the looping construct, this code is completely elimi­
nated, and its execution each loop will be completely eliminated.
Therefore, if you want fast code, you should eliminate looping con­
structs and repeat the code within the loop the desired number of times.
The cost of this move is more code. We have also seen that recursive
code can require an inordinant amount of time. Again, recursive code
merely creates hidden looping constructs that require frequent genera­
tion of stack frames prior to new function calls. The construction of
these stack frames and return from functions require time which is
often masked by the elegant appearance of the code. Usually you will
produce faster code if you figure a way to accomplish the same end
operation without calls to the executing function.
Today, we are at the very beginning of a completely new set of
microcontrollers. These machines are based on RISC (reduced instruc­
tion set computer) techniques. Do not be misled. RISC does not really
mean reduced instruction set. The instruction sets are complete and
extensive. However, the basic architecture of a RISC machine is quite
different from the older machines like those we have been working
with. One of the main differences is that the design of the machine is
to provide for the execution of one or more instructions with each
clock cycle. A standard RISC will allow almost one instruction per
clock cycle, and a super scaler architecture will allow two or more
instructions per clock cycle. This operation is enabled by the use of
instruction pipelines and multiple arithmetic logic units (ALUs). Some­
times, an instruction must use more than one clock to complete an