Page 408 - Programming Microcontrollers in C

Chapter 8

MCORE, a RISC Machine

Reduced Instruction Set Computer (RISC) machines are the new
architecture rage. First, the R in RISC is an absolute misnomer. When
first learning the M68000 machine, a CISC (Complicated Instruction
Set Computer), I found a controller with about 70 instructions. The
MMC2001, a RISC, has about 110 instructions, and it has no
instructions for the complex addressing modes that make the CISC
machine so easy to program. The RISC has its advantages though.
Most of the RISC instructions require only one clock cycle per
instruction while the CISC typically requires six clocks per instruction
with a range of two clocks to twenty-four clocks per instruction.
Therefore, a RISC chip with a 33-MHz clock will execute more than
thirty-one million instructions per second, obviously much faster than
a similar speed CISC, which would probably execute less than six
million instructions per second. However, the RISC machine will
require more instructions to execute the same program. Overall, the
RISC machine is almost always faster than the corresponding CISC,
even though the RISC requires more memory to implement the same
code.
The RISC/CISC dichotomy will be the source of nearly religious
debate until the next big architecture change is introduced. This text
is not aimed at comparison of different architectures. The goal is to
help you write code for the chips in the C language. Now the problem
becomes one of finding an appropriate compiler for the chip.
The compiler/debugger combination used in preparing the code
1 2
found in this chapter is provided by DIAB and SDS. These software

1 Diab Data, Inc., (650) 571-1700, fax (650) 571-9068, email info@ddi.com, www.ddi.com
2 Software Development Systems, Inc., (630) 368-0400, fax (630) 990-4641,
email sales@sdsi.com, www.sdsi.com

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