Page 179 - Robots Androids and Animatrons : 12 Incredible Projects You Can Build

The output of the comparator is normally high. When triggered by
the 4.5V pulse from the LED line, it outputs a negative pulse trigger.
For a comparator we are using a standard 741 operational amplifier
(op-amp).
Speech recognition can take up to 300 ms. During this time delay,
the BCD outputs remain stable and do not change. If our interface
operates too quickly, it will already be finished updating the out-
put before the SRC has a chance to update the BCD output.
To prevent this from occurring, we delay the negative pulse trig-
ger by sending it through two 555 timers (or one 556 timer) set
up in mono-stable mode. The negative pulse from the comparator
initiates a 470-ms output pulse from the first timer, which is con-
nected to the second timer. The second timer outputs a 220-ms
pulse.
The 470-ms pulse allows more than enough time for the new BCD
numbers to be outputted. When the 470-ms pulse from the first
timer goes low, it initiates an output pulse from the second timer.
This output is a positive pulse lasting approximately 220 ms. During
this time, the interface output is updated provided the error code
detector (ECD) is outputting a logic high.
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The second timer (220-ms pulse) output is connected to one input
of an AND gate. The other leg of the AND gate is connected to two
other gates (NAND and OR) that make up our ECD. The ECD is
connected to the most-significant-digit BCD number. Whenever
the BCD number is equal to 5, 6, or 7, the ECD outputs a logic low.
For all other numbers it outputs a logic high. When the output of
the ECD is positive, the positive pulse from the second timer allows
the least-significant-digit BCD number to propagate through to the
output of the interface circuit.

The output high from the ECD combined with the positive pulse
from the timer triggers a logic high from the AND gate that enables
the 74LS373 (data octal latch). With the 74LS373 enabled, any
number outputted on the lower BCD number propagates through
the 74LS373 and is latched. The four outputs of the 74LS373 are
connected to the inputs of a 4028 BCD-to-decimal decoder.
On the other hand, when the output of the ECD is low, which hap-
pens when the numbers 5, 6, and 7 are outputted, the corresponding
input to the AND gate is low. With this AND input kept low, when the
positive pulse from the second timer arrives, the output of the AND
gate will remain low, thereby keeping the 74LS373 disabled and not
allowing the lower BCD number to propagate through to the 4028.
Team LRN
Chapter seven