Page 115 - The Art of Designing Embedded Systems

102 THE ART OF DESIGNING EMBEDDED SYSTEMS

a one or back) under a nanosecond, the PCB itself assumes all of the char-
acteristics of an electronic component-one whose virtues are almost all
problematic. It’s a big subject [read High Speed Digital Design-A Hund-
book ofBluck Magic, by Howard Johnson and Martin Graham (1993 PTR
Prentice Hall, NJ) for the canonical words of wisdom on this subject], but
suffice it to say that a poorly designed PCB will create RAM reliability
problems.
Equally important are the decoupling capacitors chosen, as well as
their placement. Inadequate decoupling will create reliability problems as
well.
Modern DRAM arrays are massively capacitive. Each address line
might drive dozens of chips, with 5 to 10 pF of loading per chip. At high
speeds the drive electronics must somehow drag all of these pseudo-
capacitors up and down with little signal degradation. Not an easy job!
Again, poorly designed drivers will make your system unreliable.
Electrical noise is another reliability culprit, sometimes in unex-
pected ways. For instance, CPUs with multiplexed addreddata buses use
external address latches to demux the bus. A signal, usually named ALE
(Address Latch Enable) or AS (Address Strobe), drives the clock to these
latches. The tiniest, most miserable amount of noise on ALE/AS will
surely, at the time of maximum inconvenience, latch the data part of the
cycle instead of the address, Other signals are also vulnerable to small
noise spikes.
Unhappily, all too often common RAM tests show no problem when
hidden demons are indeed lurking. The algorithm I’ve described, as well as
most of the others commonly used, trade off speed against comprehen-
siveness. They don’t pound on the hardware in a way designed to find
noise and timing problems.
Digital systems are most susceptible to noise when large numbers of
bits change all at once. This fact was exploited for data communications
long ago with the invention of the Gray code, a variant of binary counting
where no more than one bit changes between codes. Your worst night-
mares of RAM reliability occur when all of the address and/or data bits
change suddenly from zeroes to ones.
For the sake of engineering testing, write RAM test code that exploits
this known vulnerability. Write Oxffff to Ox0000 and then to Oxffff, and
do a read-back test. Then write zeroes. Repeat as fast as your loop will let
you go.
Depending on your CPU, the worst locations might be at OxOOff and
0x0100, especially on 8-bit processors that multiplex just the lower 8 ad-
dress lines. Hit these combinations hard as well.