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216                         Chapter 9.  Error-Resilience  Video Coding  Techniques



                      7 bits        7 bits        7 bits          7 bits
                Slot 1
                Slot 2
                Slot 3
                Slot 4
                Slot 5
                Slot 6     offset 1       offset 2      offset 3

                     Stage 1       Stage 2       Stage 3          Stage 6
                Empty bit   Block 1 bit   Block 2 bit   Block 3 bit   Block 4 bit   Block 5 bit   Block 6 bit

                              Figure 9.5:  Example  of  the EREC algorithm

            the algorithm, blocks 3, 4, and 6 are completely placed into the corresponding
            slots,  with  some  leftover  space  in  those  slots.  Blocks  1,  2,  and  5,  however,
            are  only  partially  placed  in  the  corresponding  slots  and  have  some  bits  left
            to be placed in empty spaces in other slots. According to the o set sequence,
            block  1  searches  slot  2  for  empty  space,  block  2  searches  slot  3,  and  block
            5  searches  slot  6.  Both  blocks  2  and  5   nd  empty  spaces.  Thus,  in  stage  2,
            all  the  remaining  bits  from  block  2  are  placed  in  slot  3,  whereas  some  of
            the remaining bits of block 5 are placed in slot 6. Since block 1 did not  nd
            empty spaces in slot 2, then, according to the o set sequence, it searches slot
            3, and so on. By the end of stage 6, all data bits are placed in the slots. The
            decoder  operates  in  a  similar  manner.  Thus  bits  in  a  slot  are  decoded  and
            placed in a block until an end-of-block  codeword  is encountered.
               In  the  presence  of  errors,  the  resilience  provided  by  the  EREC  algorithm
            is  due  to  two  factors.  First,  each  block  starts  at  a  known  position  in  the
            bitstream (i.e., the start of the corresponding slot). Thus, in the case of loss of
            synchronization, the decoder simply jumps to the start of the next slot without
            the need for resynchronization codewords. Second, subjectively less important
            data (e.g., high-frequency DCT coe$cients) are usually placed in later stages
            of  the  algorithm.  With  the  EREC  algorithm,  most  error  propagation  e ects
            (due, for example, to missing or falsely detecting end-of-block codewords) hit
            data placed at later stages of the algorithm rather than the more important data
            at the start of  the slots.

            9.6.3.3  Reversible Variable-Length Coding (RVLC)

            Reversible  VLC  codewords  are  designed  to  be  decoded  both  in  the  forward
            and  backward  directions.  As  already  described,  when  an  error  is  detected  in
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