Page 122 - ARM 64 Bit Assembly Language

108 Chapter 4

15 mov w0, #0
16 ret
17 .size main, (. - main)

4.4 Alphabetized list of AArch64 instructions

This chapter and the previous one introduced the core set of AArch64 instructions. Most of
these instructions were introduced with the very first AArch64 processors. There are more
architectural extensions that provide special instructions for uses such as cryptography. There
are also additional instructions that compute floating point operations, called Vector Floating
Point (VFP) and NEON.

The instructions introduced so far are:

Name Page Operation
adc 86 Add with Carry
add 86 Add
adr 78 Form PC-Relative Address
adrp 78 Form PC-Relative Address to 4 KB Page
and 88 Bitwise AND
asr 91 Arithmetic shift right
b 70 Branch
bic 89 Bitwise Bit Clear
bl 73 Branch and Link
blr 73 Branch to Register and Link
br 72 Branch to Register
cbnz 76 Compare and Branch if Nonzero
cbz 76 Compare and Branch if Zero
ccmn 101 Conditional Compare Negative
ccmp 101 Conditional Compare
cinc 100 Conditional Increment
cinv 100 Conditional Invert
cls 104 Count Leading Sign Bits
clz 104 Count Leading Zeros
cmn 98 Compare Negative
cmp 98 Compare
cneg 101 Conditional Negate
csel 100 Conditional Select
cset 101 Conditional Set
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