Page 68 - ARM 64 Bit Assembly Language

CHAPTER 3

Load/store and branch instructions

The part of the computer architecture related to programming is referred to as the instruction
set architecture (ISA). The ISA is a contract between the hardware and the software. It de-
fines the set of instructions and the setofregisters that the hardware must support. How the
hardware actually implements the ISA is called the microarchitecture, and it is not defined by
the ISA. Assembly programmers can write code that will work across a spectrum of different
processor implementations. As long as the software and the hardware are both built around
the same ISA, they will be compatible. The ISA is an effective interface between hardware–
the data paths and processing elements–and software, because it creates an abstraction that
allows each side to be imagined to function independently.
The first step in learning a new assembly language is to become familiar with the ISA. For
most modern computer systems, data must be loaded in a register before it can be used for any
data processing instruction, but there are a limited number of registers. Memory provides a
place to store data that is not currently needed. Program instructions are also stored in mem-
ory and fetched into the CPU as they are needed. This chapter introduces A64, the 64-bit ISA
for AArch64 processors.

3.1 CPU components and data paths

The CPU is composed of data storage and computational components connected together
by a set of buses, or wires. The most important components of the CPU are the registers,
where data is stored, and the arithmetic and logic unit (ALU), where arithmetic and logical
operations are performed on the data. Many CPUs also have dedicated hardware units for
multiplication and/or division. Fig. 3.1 shows a conceptual view of the major components
of an AArch64 CPU and the buses that connect the components together. These buses pro-
vide pathways for the data to move between the computational and storage components. The
organization of the components and buses in a CPU govern what types of operations can be
performed.

The set of instructions and addressing modes available on the AArch64 processor is closely
related to the architecture shown in Fig. 3.1. The architecture provides for certain operations
to be performed efficiently, and this has a direct relationship to the types of instructions that
are supported.

ARM 64-Bit Assembly Language
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