Page 255 - Complete Wireless Design

Frequency Synthesizer Design

254 Chapter Five

DC correction voltage at its output into the low-pass PLL loop filter if these two
frequencies differ. This filter eliminates any AC variations and noise products,
placing the now pure DC directly into the VCO’s frequency control input. The
all-important loop filter is required to filter powerful phase comparator con-
stituents at the comparison frequency (f ) and its harmonics, since if these
COM
responses actually got through to the VCO they would adversely modify its sta-
bility. The varactor diode’s bias within the VCO is affected by this DC control
voltage, which immediately forces the VCO back on frequency if it has drifted
off. These actions permit a frequency source to be adjustable over many dis-
crete frequencies, but with the stability of the crystal oscillator reference.
The adjustable N frequency divider of the PLL is usually controlled by the
operator through a front radio panel knob, or automatically by system com-
mands. A microprocessor will normally supply digital control words to the PLL
through a serial, but sometimes even a parallel, bus (see below) to change fre-
quency. The microprocessor can also be employed to decode and drive display
circuits to inform the radio operator of the exact channel of transmit or receive.
Premixing (Fig. 5.2) of a synthesizer can be used to obtain a higher fre-
quency from a lower frequency PLL. The output of the PLL and a crystal oscil-
lator can be fed into a mixer, and filtered by a bandpass filter to attain the sum
of these two frequencies. Frequency multiplying of the PLL’s output, at the
expense of higher phase noise and degraded frequency channel resolution, can
also be utilized to increase the PLL’s output frequency.
A widespread manual PLL tuning scheme is shown in the circuit of Fig. 5.3.
It has a shaft encoder, a microprocessor, the display with its driver, and a PLL
chip with loop filter and VCO. Rotated by the radio operator, the tuning knob
turns an optical or magnetic encoder that has two voltage outputs, A and B.
The A output is a square wave in quadrature phase (90 degree phase shifted)
to the B square wave output. The A output is connected directly to the micro-
processor’s interrupt line; when the A output from the encoder produces a
falling edge, an interrupt will occur. The microprocessor will then immediate-
ly look at the B output to see if it is a 1. If it is, then the microprocessor con-
siders that the knob has been rotated clockwise. The microprocessor will then
increment the PLL’s N divider by 1, increasing the output frequency, and
update the frequency display appropriately. However, if B is a 0, then the
microprocessor considers that the knob has been rotated counterclockwise,
and the microprocessor decrements the PLL’s N divider by 1, decreasing its
output frequency.
Even though the PLL circuit in general obviously has many advantages,
such as a much higher possible operating frequency than a crystal oscillator,
is tunable in discrete steps, and is as stable as the reference source (which is
usually a simple 10-MHz crystal oscillator), PLLs are far inferior to crystal
sources when it comes to phase noise specifications. This can be a problem in
digital wireless communications.
Most PLL chips are of the charge-pump type (Fig. 5.4). The charge pump
outputs a current of steady amplitude, but with changeable duty cycle and

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