Page 260 - Complete Wireless Design

Frequency Synthesizer Design

Frequency Synthesizer Design 259

are described in the Wireless Design Software section, and both are located on
the CD ROM disk included with this book.
The first place to begin in the design of a PLL frequency synthesizer circuit
is in deciding on what we want our center frequency, frequency swing (mini-
mum and maximum frequencies), speed (lock time), and channel resolution
(spacing) to be, then select the appropriate PLL chip, VCO, and reference oscil-
lator that can safely, economically, and repeatedly meet these criteria.
The following list should be completed so that the complete specifications of
the PLL circuit of Fig. 5.4 can be clearly defined:

F HZ. The maximum output frequency required. Must never be
MAX
more than the VCO was designed to handle, along with about 20 percent
VCO frequency excess for a safety margin. Using a VCO with less tuning
bandwidth decreases its phase noise.
F Hz. The minimum output frequency required. Must never be
MIN
less than the VCO was designed to handle, along with about 20 percent VCO
frequency excess for a safety margin. Using a VCO with less tuning
bandwidth decreases its phase noise.
F MHz. Equal to F ; must be a multiple of F .
F
OUT MAX MIN COM
K MHz/V. Normally between 5 and 70 MHz/V. K is the VCO’s
VCO VCO
gain (sensitivity) measured in megahertz per volt, and is the amount of
frequency deviation, in megahertz, that the VCO will travel when 1 VDC is
placed at its DC frequency control input.
K mA/2 . Charge pump gain (K ) is measured in milliamperes
per 2 , and should be chosen at the highest value the PLL chip will allow in
order to obtain the lowest phase noise at the VCO’s output. This value will
normally be either 1 or 5 mA/2 , and is typically selectable. A charge pump
with a gain of 5 mA/2 would be preferred over a charge pump with 1 mA/2
if current consumption is not an issue. This charge pump gain value will also
vary with the charge pump voltage supply.
F kHz. Normally equal to the channel spacing. F and F
COM OUT REF
must be a multiple of F . Sometimes it may be required to use an F that
COM COM
is a certain fraction of the channel spacing because of the PLL’s internal
prescaler. The higher F is, the better the phase noise of the PLL.
COM
F kHz. The loop bandwidth of the PLL filter. F should be as
C C
narrow as possible to lessen spurious noise, but this will decrease switching
speed. Normally F should be between 1 and 20 kHz, but must be at least
C
1/20 F (National Semiconductor recommends a 2-kHz F if lock time does
COM C
not matter). The choice of F will always be a compromise between reference
C
sideband suppression and lock time—select a loop F to just meet the lock
C
requirement, but with an acceptable margin.
(phase margin) degrees. Normally select a value between 30 and
70 degrees for the loop filter. The higher the phase margin, the higher the
PLL’s stability, but the slower will be its lock time. Choose a phase margin of

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