Page 263 - Complete Wireless Design

Frequency Synthesizer Design

262 Chapter Five

3, 4. GND at Pins 3 and 4 are for the charge pump and for the analog circuits
respectively. Both can be short-circuited together and attached as
directly as possible to system ground.
5. f should be AC-shorted to ground through a 100-pF capacitor.
IN
6. f accepts the signal from the VCO’s output through a series 20- to 200-
IN
ohm resistor. The series resistor, whose value depends on the VCO’s out-
put power, will lower the power into the preselector, allowing most of this
energy to be delivered to the load.
7. V 1 pin is the heavily bypassed DC analog power supply voltage input.
cc
The input voltage for this particular chip may be anywhere between 2.3
and 5.5 V; but must equal pin 15’s V 2 voltage.
cc
8. OSC is the reference oscillator input for a CMOS 100-kilohm output
IN
resistance clock oscillator. A clean crystal clock input is vital for a low-
phase-noise PLL output.
9. GND is digital ground. It should reach system ground by as direct a route
as possible.
10. CE is the chip enable pin when power is down for power-saving operation.
It can be tied to V if this feature is not required.
CC
11. CLK is an input that accepts a CMOS clock signal from the channel select
microcontroller for clocking data into pin 12.
12. DATA input accepts data from the microcontroller for the R counter, the N
counter, and the function latch (which controls phase detector polarity,
fast-lock modes, F /LD, counter reset, CP tristate, test modes, etc.), with
o
the last two bits (control bits) informing the PLL as to whether the data
should be sent to the R counter (0, 0), the N counter (1, 0), or the function
latch (0,1) on command of pin 13, LE.
13. LE (load enable) pin controls when the PLL’s registers will send data to
the R, N, or function latches, depending on the control bits.
14. F /LD is an output pin that can typically be used as a lock detect (LD) out-
o
put pin into a microprocessor, or into some out-of-lock alarm. A HIGH will
be output when the PLL is in lock (on advanced PLL chips, such as with
the National line, a trace may be taken from the lock detect (LD) pin back
to the microprocessor. The pin, if digital lock detect is chosen by program-
ming the proper PLL register, will output a HIGH as long as the VCO out-
put frequency is locked. This HIGH or LOW signal can then be exploited
by the microprocessor to indicate an unlocked condition by an LED warn-
ing on a display, or as an automatic shutdown of a runaway transmitter).
15. V 2 is the digital power supply voltage input pin, and should be tied to
CC
pin 7, which is the analog power supply input.
16. V is the power supply for the charge pump circuit, and must be greater
p
than V . (The DC control voltage into the VCO will always be a few
CC

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