Page 267 - Complete Wireless Design

Frequency Synthesizer Design

266 Chapter Five

1. Confirm that the reference oscillator is functioning, and at the proper power
level and frequency.
2. Confirm that R is not at too high a value back into the N divider, and that
o
C still has a low reactance (Fig. 5.4).
C
3. Confirm that the data input into the PLL chip is correct, such as LE, the
binary serial input data, and the data clock input.
4. Confirm that poor physical PCB layout is not causing reference spurs and
added noise outputs.
5. Confirm that the VCO will never be presented with a DC tuning voltage of
0 V (due to varactor nonlinearities), and establish that the VCO is operated
within its designed tuning range, with adequate headroom for the inevitable
overshoot while locking of approximately 15 to 20 percent above and below
the required f and f frequencies.
MIN MAX
A complete synthesizer stage for a wideband transmitter or receiver is
shown in Fig. 5.10. Not only are the PLL chip, reference oscillator, loop filter,
and VCO shown, but so is the VCO gain amplifier used to increase the tuning
voltage for the wideband VCO, the 6 dB pad to supply a closer-to-50-ohm load
to the VCO’s output, a buffer amplifier to furnish gain for a higher output
amplitude with a low S for isolation, a VCO harmonic filter to clean up the
12
synthesizer’s output, and another pad to assure a 50-ohm termination for the
harmonic filter and the next stage, a double-balanced mixer (DBM).

5.2 Direct Digital Synthesis
Direct digital synthesis (DDS) is a relatively new technique that decreases the
cost and complexity of a frequency synthesizer that must have a very tight fre-
quency resolution of up to 1 Hz (or less), thus giving the feel of analog LC fine
tuning. DDS synthesizers, like PLLs, are supplied in small surface mount
integrated circuits, along with one or more support ICs and multiple support
components.
One method for generating DDS frequencies (Fig. 5.11) functions by using a
crystal oscillator reference as the CLOCK, then calculating, in the PHASE
ACCUMULATOR, the discrepancy between this reference frequency and the
actual frequency the wireless device would like to generate. The PHASE
ACCUMULATOR will then calculate the proper address to send to the WAVE-
FORM ROM or RAM sine-wave lookup table for the frequency we want to gen-
erate, which forwards the appropriate discrete digital representation of the
desired signal into the D/A CONVERTER. The still rough, stepped waveform
is sent into a high-quality low-pass filter (LPF) to remove any spurious prod-
ucts, outputting a high-quality, artificially constructed analog sine-wave.
All of today’s DDS synthesizers have very limited maximum frequency
ranges. This forces many designs to go with a hybrid DDS/PLL scheme to
increase the range to higher levels. Also, quantization noise can be a signifi-

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