Page 259 - Complete Wireless Design

Frequency Synthesizer Design

258 Chapter Five

N is not permitted to be less than P(P 1), and if N is less than P(P 1), then
B A, with:
N f OUT
B and A N BP and N
P f
COM
The final outcome of using these dual-modulus prescalers, which are a part
of the N divider, in PLLs is that it becomes possible to control the division ratio
into the phase comparator in steps of 1(N), as opposed to the huge steps of 32
or 33 in a fixed-modulus 32 or 33 prescaler. This N value must always be an
integer, with the largest N value being determined by the size of the B counter,
since N P (B A). Dual-modulus prescalers will, however, have certain ille-
gal divide ratios, in which specific frequencies cannot be generated. If a par-
ticular N value results in a B register that is smaller than the A register, this
will not be allowed, since B must be greater than or equal to A for a legal
divide ratio. In other words, not all N values are allowed with a dual-modulus
prescaler–equipped PLL. The tradeoff between having certain frequencies
that are impossible to generate is that we can obtain better frequency resolu-
tion at the PLL’s output than would normally be possible. However, if it is
essential that certain frequencies be generated by the PLL dual-modulus
prescaler (since N must equal (P 1)(A P)(B A) to be a legal divide ratio),
then a legal divide ratio check should be performed by using National’s Easy
PLL or National’s Code Loader program.

5.1.2 Designing phase-locked loops
The design of PLL frequency synthesizer circuits, until recently, was fraught
with complications and uncertain results. However, PLL chip companies, pri-
marily National Semiconductor, have released information that makes the
design of a frequency synthesizer much more simplified than in the past.
National Semiconductor has also released two different PLL design programs
that almost completely automate the PLL design task. Two of these programs

Figure 5.5 A dual-modulus prescaler for a PLL.

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