Page 110 - Electrical Engineering Dictionary

bus acquisition the point at which a bus controller the logic that coordinates
bus arbiter grants bus access to a specific re- the operation of a bus.
questor. A device connected to the bus will issue
a bus request when it wishes to use the bus.
bus arbiter (1) the unit responsible for The controller will arbitrate among the cur-
choosing which subsystem will be given con- rent requests and grant one requester access.
trol of the bus when two or more requests The bus controller also monitors possible er-
for control of the bus happen simultaneously. rors, such as use of an improper address, a
Some bus architectures, such as Ethernet, do device not releasing the bus, and control er-
not require a bus arbiter. rors.
(2) the device that performs bus arbitra- Bus control logic may reside in multiple
tion. See also bus arbitration. subsystems, distributed control, or may be
centralized in a subsystem. See also bus
bus arbitration the process of determin- cycle, bus master.
ing which competing bus master should be
granted control of the bus. The act of choos- bus cycle the sequence of steps involved
ing which subsystem will be given control of in a single bus operation. A complete bus cy-
the bus when two or more requests for control cle may require that several commands and
of the bus happen simultaneously. The ele- acknowledgments are sent between the sub-
ment that make the decision is usually called systems in addition to the actual data that is
the bus arbiter. See also bus priority. sent.
For example,
bus architecture a computer system ar- 1. the would-be bus master requests
chitecture in which one or more buses are access to the bus
used as the communication pathway between 2. the bus controller grants the requester
I/Odevicecontrollers, theCPU,andmemory. access to the bus as bus master
See also channel architecture. 3. the bus master issues a read command
with the read address
bus bandwidth (1) the data transfer rate 4. the bus slave responds with data
in bits per second or bytes per second. In 5. the master acknowledges receipt of the
some instances the bandwidth average rate data
is given and in others the maximum rate is 6. the bus master releases the bus.
given. It is approximately equal to the width The first two steps may be overlapped with
of the data bus, multiplied by the transfer rate the preceding data transfer.
in bus data words per second. Thus a 32 bit See also bus controller, bus master.
data bus, transferring 25 million words per
second (40 ns clock) has a bandwidth of 800 bus differential relay a differential relay
Mb/s. specifically designed to protect high power
The useful bandwidth may be lowered by buses with multiple inputs.
the time to first acquire the bus and possibly
transfer addresses and control information. bus driver the circuits that transmit a
(2) the transfer rate that is guaranteed that signal across a bus.
no user will exceed.
bus grant an output signal from a pro-
bus bar a heavy conductor, typically with- cessor indicating that the processor has relin-
out insulation and in the form of a bar of rect- quished control of the bus to a DMA device.
angular cross-section.
bus hierarchy a network of busses linked
bus broadcast See broadcast. together (usually multiple smaller busses

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