Page 111 - Electrical Engineering Dictionary

connected to one or more levels of larger bus priority rules for deciding the prece-
busses), used to increase the number of el- dence of devices in having bus requests hon-
ements that may be connected to a high- ored.
performance bus structure. Devices issue requests on one of several
bus request lines, each with a different bus
bus idle the condition that exists when priority. A high priority request then “wins”
the bus is not in use. over a simultaneous request at a lower prior-
ity.
bus impedance matrix See Z-bus.
The request grant signals then “daisy
chains” through successive devices along the
bus interface unit in modern CPU im-
bus or is sent directly to devices in appropri-
plementations, the module within the CPU
ate order. The requesting device closest to
directly responsible for interactions between
the bus controller then accepts the grant and
the CPU and the memory bus.
blocks its propagation along the bus.
Buses may have handle interrupts and di-
bus line one of the wires or conductors
rect memory accesses with separate priority
that constitute a bus. A bus line may be used
systems.
for data, address, control, or timing.
bus protocol (1) a set of rules that two
bus locking the action of retaining con-
parties use to communicate.
trol of a bus after an operation which would
(2) the set of rules that define precisely
normally release the bus at completion. In
the bus signals that have to be asserted by the
themanipulationofmemorylocks, amemory
master and slave devices in each phase of a
read must be followed by a write to the same
bus operation.
location with a guarantee of no intervening
operation. The bus must be locked from the
bus request an input signal to a processor
initial read until after the update write to give
that requests access to the bus; a hold signal.
an indivisible read/write to memory.
Competing bus requests are resolved by the
bus controller. See also bus controller.
bus master a bus device whose request
is granted by the bus controller and thereby
gains control of the bus for one or more cy- bus slave a device that responds to a re-
cles or transfers. The bus master may always quest issued by the bus master. See also bus
master.
reside with one subsystem, or may be trans-
ferred between subsystems, depending on the
architecture of the bus control logic. See also bus snooping the action of monitoring
bus controller, bus cycle. all traffic on a bus, irrespective of the ad-
dress. Bus snooping is required where there
bus owner the entity that has exclusive are several caches with the same or overlap-
access to a bus at a given time. ping address ranges. Each cache must then
“snoop” on the bus to check for writes to ad-
bus phase a term applying especially to dresses it holds; conflicting addresses may be
synchronous buses, controlled by a central updated or may be purged from the cache.
clock, with alternating “address” and “data” Bus snooping is also useful as a diagnostic
transfers. A single transfer operation re- tool.
quires the two phases to transfer first the ad-
dress and then the associated data. Bus ar- bus state triggering a data acquisition
bitration may be overlapped with preceding mode initiated when a specific digital code is
operations. selected.

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2000 by CRC Press LLC