Page 114 - Electrical Engineering Dictionary

A hit occurs when a reference can be sat-
isfied by the cache; otherwise a miss occurs.
C The proportion of hits (relative to the total
numberofmemoryaccesses)isthehitratioof
the cache, and the proportion of misses is the
miss ratio. See also code cache, data cache,
direct mapped cache, fully associative cache,
c common symbol for speed of light in set associative cache, and unified cache.
free space. c = 3 × 10 10 cm/s.

cache aliasing a situation where two or
common notation for FET gate-to-
C GD
more entries (typically from different virtual
drain capacitance.
addresses) in a cache correspond to the same
address(es) in main memory. Considered un-
common notation for FET gate-to-
C GS
desirable, as it may lead to a lack of consis-
source capacitance.
tency (coherence) when data is written back
to main memory.
C-band microwave frequency range,
3.95-5.85 Ghz.
cache block the number of bytes trans-
C-element a circuit used in an asyn- ferred as one piece when moving data be-
chronous as an interconnect circuit. The tween levels in the cache hierarchy or be-
function of this circuit is to facilitate the tween main memory and cache). The term
handshaking communication protocol be- line is sometimes used instead of block. Typ-
tween two functional blocks. ical block size is 16-128 bytes and typical
cache size is 1-256 KB. The block size is
cable an assembly of insulated conduc- chosen so as to optimize the relationship of
tors, either buried or carried on poles (aerial the “cache miss ratio,” the cache size, and the
cable). block transfer time.

cable limiter a cable connector that con-
cache coherence the problem of keeping
tains a fuse. Cable limiters are used to pro-
consistent the values of multiple copies of a
tect individual conductors that are connected
single variable, residing either in main mem-
in parallel on one phase of a circuit.
ory and cache in a uniprocessor, or in dif-
ferent caches in a multiprocessor computer.
cable tray a specialized form of raceway
In a uniprocessor, the problem may arise if
used to hold insulated electric power cables
the I/O system reads and writes data into the
in a building.
main memory, causing the main memory and
cache data to be inconsistent, or if there is
cache an intermediate memory store hav-
aliasing. Old (stale) data could be output
ing storage capacity and access times some-
if the CPU has written a newer value in the
where in between the general register set and
cache, and this has not been transported to
main memory. The cache is usually invisi-
the memory. Also, if the I/O system has in-
ble to the programmer, and its effectiveness
put a new value to main memory, new data
comes from being able to exploit program lo-
would reside in main memory, but not in the
cality to anticipate memory-access patterns
cache.
and to hold closer to the CPU: most accesses
to main memory can be satisfied by the cache,
thus making main memory appear to be faster cache hit when the data referenced by the
than it actually is. processor is already in the cache.
c
2000 by CRC Press LLC