Page 39 - Electrical Engineering Dictionary

2. A full decoder takes N bits and asserts
N
one of 2 outputs, and is used within mem-
ories (often within RAM chips themselves).
address error an exception (error inter-
rupt) caused by a program’s attempt to access
unaligned words or long words on a proces-
Transformer with additive polarity. sor that does not accommodate such requests.
The address error is detected within the CPU.
of errors in the channel can be modeled as This contrasts with problems that arise in ac-
the addition of random noise with a Gaus- cessing the memory itself, where a logic cir-
sian distribution and a constant (white) power cuit external to the CPU itself must detect and
spectrum. See also thermal noise. signal the error to cause the CPU to process
the exception. Such external problems are
address a unique identifier for the place called bus errors.
where information is stored (as opposed to
the contents actually stored there). Most stor- address field the portion of a program
age devices may be regarded by the user as a instruction word that holds an address.
linear array, such as bytes or words in RAM
or sectors on a disk. The address is then just address generation interlock (AGI) a
an ordinal number of the physical or logical mechanism to stall the pipeline for one cycle
position. In some disks, the address may be when an address used in one machine cycle
compound, consisting of the cylinder or track is being calculated or loaded in the previous
and the sector within that cylinder. cycle. Address generation interlocks cause
In more complex systems, the address the CPU to be delayed for a cycle. (AGIs
may be a “name” that is more relevant to the on the Pentium are even more important to
user but must be translated by the underlying remove, since two execution time slots are
software or hardware. lost).

address aliasing See cache aliasing. address locking a mechanism to protect
a specific memory address so that it can be
address bus the set of wires or tracks accessed exclusively by a single processor.
on a backplane, printed circuit board, or in-
tegrated circuit to carry binary address sig- address map a table that associates a base
nals between different parts of a computer. address in main memory with an object (or
The number of bits of address bus (the width page) number.
of the bus) determines the maximum size of
memory that can be addressed. Modern mi- address mapping the translation of vir-
crochips have 32 address lines, thus 4 giga- tual address into real (i.e., physical) ad-
bytes of main memory can be accessed. dresses for memory access. See also virtual
memory.
address decoder logic that decodes an
address. address register a register used primarily
1. A partial decoder responds to a small to hold the address of a location in memory.
range of addresses and is used when recog- The location can contain an operand or an
nizing particular device addresses on an I/O executable instruction.
address bus, or when recognizing that ad-
dresses belong to a particular memory mod- address size prefix a part of a machine
ule. instruction that provides information as to the

c
2000 by CRC Press LLC