Page 260 - Engineering Digital Design

PROBLEMS 231

5.1 Compress the following function into a first-order K-map of axis A, and loop out a
gate minimum expression by using XOR-type patterns in minterm code. Next, obtain
the SOP minimum from the same K-map and compare the gate/input tallies for both
the XOR and SOP forms. Finally, construct the logic circuits for the XOR and SOP
results assuming that the inputs and output are all active high. What do you conclude
from these comparisons?

E = AXY + AXY + AY

5.2 The output F of a logic circuit is a function of three inputs A, B, and C. The output
goes active under any of the following conditions as read in the order ABC:

All inputs are logic 1
An odd number of inputs are logic 1
None of the inputs are logic 1

(a) Construct a truth table for output function F and inputs ABC.
(b) Map the result in a second-order K-map and extract a gate-minimum expression
by using XOR-type patterns.
(c) Further compress this function into a first-order K-map of axis A and again extract
a gate-minimum expression by using XOR-type patterns. Compare the result with
that of (b).
(d) Finally, place this function in a conventional (1's and O's) K-map and extract
minimum two-level SOP and POS logic expressions. By using the gate/input tally
(exclusive of inverters), compare the results with those of (b) and (c). What do
you conclude from this comparison?
5.3 Compress the following function into a second-order K-map with axes as indicated
and extract a gate-minimum expression for each set of axes by using XOR patterns.
Use the gate/input tally, exclusive of possible inverters, to compare this result with the
minimum expressions for the two-level SOP and POS results. What do you conclude
from this comparison? What is the gate delay level for the XOR pattern results? (Hint:
It will be helpful to first plot this function into a conventional 1's and O's K-map.)

F(W, X, Y, Z) = J^m(0, 2, 5, 7, 9, 11, 12)

(a) Axes W, X
(b) Axes 7, Z
(c) Axes X, Y

5.4 Shown in Fig. P5.1 are six EV K-maps that contain XOR-type patterns and that
represent two and three levels of compression. Use minterm code to loop out a gate-
minimum cover for each by using XOR patterns (where appropriate). For comparison,
loop out a minimum two-level SOP cover for each and compare their relative com-
plexity by using the gate/input tally exclusive of possible inverters. Also, as part of
the comparison, comment on the fan-in requirements for each.